| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_IMX8M=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x40200000 |
| Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 4 | CONFIG_SPL_GPIO=y |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 5 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 6 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 7 | CONFIG_SYS_MALLOC_F_LEN=0x10000 |
| 8 | CONFIG_ENV_SIZE=0x10000 |
| 9 | CONFIG_ENV_OFFSET=0x3C0000 |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 10 | CONFIG_DM_GPIO=y |
| Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 11 | CONFIG_DEFAULT_DEVICE_TREE="phycore-imx8mm" |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 12 | CONFIG_SPL_TEXT_BASE=0x7E1000 |
| 13 | CONFIG_TARGET_PHYCORE_IMX8MM=y |
| 14 | CONFIG_SPL_MMC_SUPPORT=y |
| 15 | CONFIG_SPL_SERIAL_SUPPORT=y |
| Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 16 | CONFIG_SPL_DRIVERS_MISC=y |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 17 | CONFIG_SPL=y |
| 18 | CONFIG_ENV_OFFSET_REDUND=0x3E0000 |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 19 | CONFIG_FIT=y |
| 20 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 21 | CONFIG_SPL_LOAD_FIT=y |
| 22 | CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" |
| 23 | CONFIG_OF_SYSTEM_SETUP=y |
| 24 | CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" |
| 25 | CONFIG_DEFAULT_FDT_FILE="oftree" |
| 26 | CONFIG_BOARD_LATE_INIT=y |
| 27 | CONFIG_SPL_BOARD_INIT=y |
| 28 | CONFIG_SPL_SEPARATE_BSS=y |
| Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 29 | CONFIG_SPL_I2C=y |
| Simon Glass | e91ac4c | 2021-07-10 21:14:24 -0600 | [diff] [blame] | 30 | CONFIG_SPL_POWER=y |
| Simon Glass | 1ba1d4e | 2021-07-10 21:14:28 -0600 | [diff] [blame] | 31 | CONFIG_SPL_WATCHDOG=y |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 32 | CONFIG_HUSH_PARSER=y |
| 33 | CONFIG_SYS_PROMPT="u-boot=> " |
| 34 | # CONFIG_CMD_EXPORTENV is not set |
| 35 | # CONFIG_CMD_IMPORTENV is not set |
| 36 | # CONFIG_CMD_CRC32 is not set |
| 37 | CONFIG_CMD_EEPROM=y |
| Tom Rini | faed567 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 38 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 |
| 39 | CONFIG_SYS_EEPROM_SIZE=4096 |
| 40 | CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 |
| 41 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 42 | CONFIG_CMD_FUSE=y |
| 43 | CONFIG_CMD_GPIO=y |
| 44 | CONFIG_CMD_I2C=y |
| 45 | CONFIG_CMD_MMC=y |
| 46 | CONFIG_CMD_DHCP=y |
| 47 | CONFIG_CMD_MII=y |
| 48 | CONFIG_CMD_PING=y |
| 49 | CONFIG_CMD_CACHE=y |
| 50 | CONFIG_CMD_REGULATOR=y |
| 51 | CONFIG_CMD_EXT2=y |
| 52 | CONFIG_CMD_EXT4=y |
| 53 | CONFIG_CMD_EXT4_WRITE=y |
| 54 | CONFIG_CMD_FAT=y |
| 55 | CONFIG_OF_CONTROL=y |
| 56 | CONFIG_SPL_OF_CONTROL=y |
| 57 | CONFIG_ENV_OVERWRITE=y |
| 58 | CONFIG_ENV_IS_IN_MMC=y |
| 59 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
| 60 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 61 | CONFIG_SYS_MMC_ENV_DEV=2 |
| 62 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 63 | CONFIG_SPL_DM=y |
| 64 | CONFIG_SPL_CLK_COMPOSITE_CCF=y |
| 65 | CONFIG_CLK_COMPOSITE_CCF=y |
| 66 | CONFIG_SPL_CLK_IMX8MM=y |
| 67 | CONFIG_CLK_IMX8MM=y |
| 68 | CONFIG_MXC_GPIO=y |
| 69 | CONFIG_DM_I2C=y |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 70 | CONFIG_MISC=y |
| 71 | CONFIG_I2C_EEPROM=y |
| 72 | CONFIG_SYS_I2C_EEPROM_ADDR=0x51 |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 73 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 |
| Teresa Remmet | 82750c2 | 2020-08-21 09:55:53 +0200 | [diff] [blame] | 74 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 75 | CONFIG_MMC_IO_VOLTAGE=y |
| 76 | CONFIG_MMC_UHS_SUPPORT=y |
| 77 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 78 | CONFIG_MMC_HS400_SUPPORT=y |
| 79 | CONFIG_FSL_ESDHC_IMX=y |
| 80 | CONFIG_PHYLIB=y |
| 81 | CONFIG_PHY_TI_DP83867=y |
| 82 | CONFIG_DM_ETH=y |
| 83 | CONFIG_PHY_GIGE=y |
| 84 | CONFIG_FEC_MXC=y |
| 85 | CONFIG_MII=y |
| 86 | CONFIG_PINCTRL=y |
| 87 | CONFIG_SPL_PINCTRL=y |
| 88 | CONFIG_PINCTRL_IMX8M=y |
| 89 | CONFIG_DM_REGULATOR=y |
| 90 | CONFIG_DM_REGULATOR_FIXED=y |
| 91 | CONFIG_DM_REGULATOR_GPIO=y |
| 92 | CONFIG_MXC_UART=y |
| 93 | CONFIG_SYSRESET=y |
| 94 | CONFIG_SPL_SYSRESET=y |
| 95 | CONFIG_SYSRESET_PSCI=y |
| 96 | CONFIG_SYSRESET_WATCHDOG=y |
| 97 | CONFIG_DM_THERMAL=y |
| 98 | CONFIG_IMX_WATCHDOG=y |