| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Board-specific early ddr/sdram init. |
| 4 | * |
| 5 | * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> |
| Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame^] | 8 | .equ PPMCR0, 0xfc04002d |
| Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 9 | .equ MSCR_SDRAMC, 0xec094060 |
| 10 | .equ MISCCR2, 0xec09001a |
| 11 | .equ DDR_RCR, 0xfc0b8180 |
| 12 | .equ DDR_PADCR, 0xfc0b81ac |
| 13 | .equ DDR_CR00, 0xfc0b8000 |
| 14 | .equ DDR_CR06, 0xfc0b8018 |
| 15 | .equ DDR_CR09, 0xfc0b8024 |
| 16 | .equ DDR_CR40, 0xfc0b80a0 |
| 17 | .equ DDR_CR45, 0xfc0b80b4 |
| 18 | .equ DDR_CR56, 0xfc0b80e0 |
| 19 | |
| 20 | .global sbf_dram_init |
| 21 | .text |
| 22 | |
| 23 | sbf_dram_init: |
| 24 | /* CD46 = DDR on */ |
| 25 | move.l #PPMCR0, %a1 |
| 26 | move.b #46, (%a1) |
| 27 | |
| 28 | /* stmark 2, max drive strength */ |
| 29 | move.l #MSCR_SDRAMC, %a1 |
| 30 | move.b #1, (%a1) |
| 31 | |
| 32 | /* |
| 33 | * use cpu clock, seems more realiable |
| 34 | * |
| 35 | * DDR2 clock is serviced from DDR controller as input clock / 2 |
| 36 | * so, if clock comes from |
| 37 | * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) |
| 38 | * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) |
| 39 | * |
| 40 | * . |
| 41 | * / \ DDR2 can't be clocked lower than 125Mhz |
| 42 | * / ! \ DDR2 init must pass further i/dcache enable test |
| 43 | * /_____\ |
| 44 | * WARNING |
| 45 | */ |
| 46 | |
| 47 | /* cpu / 2 = 125 Mhz for 480 Mhz pll */ |
| 48 | move.l #MISCCR2, %a1 |
| 49 | move.w #0xa01d, (%a1) |
| 50 | |
| 51 | /* DDR force sw reset settings */ |
| 52 | move.l #DDR_RCR, %a1 |
| 53 | move.l #0x00000000, (%a1) |
| 54 | move.l #0x40000000, (%a1) |
| 55 | |
| 56 | /* |
| 57 | * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, |
| 58 | * 500/700 mV are ok |
| 59 | */ |
| 60 | move.l #DDR_PADCR, %a1 |
| 61 | move.l #0x01030203, (%a1) /* as freescale tower */ |
| 62 | |
| 63 | move.l #DDR_CR00, %a1 |
| 64 | move.l #0x01010101, (%a1)+ /* 0x00 */ |
| 65 | move.l #0x00000101, (%a1)+ /* 0x04 */ |
| 66 | move.l #0x01010100, (%a1)+ /* 0x08 */ |
| 67 | move.l #0x01010000, (%a1)+ /* 0x0C */ |
| 68 | move.l #0x00010101, (%a1)+ /* 0x10 */ |
| 69 | move.l #DDR_CR06, %a1 |
| 70 | move.l #0x00010100, (%a1)+ /* 0x18 */ |
| 71 | move.l #0x00000001, (%a1)+ /* 0x1C */ |
| 72 | move.l #0x01000001, (%a1)+ /* 0x20 */ |
| 73 | move.l #0x00000100, (%a1)+ /* 0x24 */ |
| 74 | move.l #0x00010001, (%a1)+ /* 0x28 */ |
| 75 | move.l #0x00000200, (%a1)+ /* 0x2C */ |
| 76 | move.l #0x01000002, (%a1)+ /* 0x30 */ |
| 77 | move.l #0x00000000, (%a1)+ /* 0x34 */ |
| 78 | move.l #0x00000100, (%a1)+ /* 0x38 */ |
| 79 | move.l #0x02000100, (%a1)+ /* 0x3C */ |
| 80 | move.l #0x02000407, (%a1)+ /* 0x40 */ |
| 81 | move.l #0x02030007, (%a1)+ /* 0x44 */ |
| 82 | move.l #0x02000100, (%a1)+ /* 0x48 */ |
| 83 | move.l #0x0A030203, (%a1)+ /* 0x4C */ |
| 84 | move.l #0x00020708, (%a1)+ /* 0x50 */ |
| 85 | move.l #0x00050008, (%a1)+ /* 0x54 */ |
| 86 | move.l #0x04030002, (%a1)+ /* 0x58 */ |
| 87 | move.l #0x00000004, (%a1)+ /* 0x5C */ |
| 88 | move.l #0x020A0000, (%a1)+ /* 0x60 */ |
| 89 | move.l #0x0C00000E, (%a1)+ /* 0x64 */ |
| 90 | move.l #0x00002004, (%a1)+ /* 0x68 */ |
| 91 | move.l #0x00000000, (%a1)+ /* 0x6C */ |
| 92 | move.l #0x00100010, (%a1)+ /* 0x70 */ |
| 93 | move.l #0x00100010, (%a1)+ /* 0x74 */ |
| 94 | move.l #0x00000000, (%a1)+ /* 0x78 */ |
| 95 | move.l #0x07990000, (%a1)+ /* 0x7C */ |
| 96 | move.l #DDR_CR40, %a1 |
| 97 | move.l #0x00000000, (%a1)+ /* 0xA0 */ |
| 98 | move.l #0x00C80064, (%a1)+ /* 0xA4 */ |
| 99 | move.l #0x44520002, (%a1)+ /* 0xA8 */ |
| 100 | move.l #0x00C80023, (%a1)+ /* 0xAC */ |
| 101 | move.l #DDR_CR45, %a1 |
| 102 | move.l #0x0000C350, (%a1) /* 0xB4 */ |
| 103 | move.l #DDR_CR56, %a1 |
| 104 | move.l #0x04000000, (%a1)+ /* 0xE0 */ |
| 105 | move.l #0x03000304, (%a1)+ /* 0xE4 */ |
| 106 | move.l #0x40040000, (%a1)+ /* 0xE8 */ |
| 107 | move.l #0xC0004004, (%a1)+ /* 0xEC */ |
| 108 | move.l #0x0642C000, (%a1)+ /* 0xF0 */ |
| 109 | move.l #0x00000642, (%a1)+ /* 0xF4 */ |
| 110 | move.l #DDR_CR09, %a1 |
| 111 | tpf |
| 112 | move.l #0x01000100, (%a1) /* 0x24 */ |
| 113 | |
| 114 | move.l #0x2000, %d1 |
| 115 | bsr asm_delay |
| 116 | |
| 117 | |
| 118 | rts |