Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 62cdac18dd063a4927f4a63fc258dab47b9747a3 / . / configs / puma-rk3399_defconfig
blob: 964464ac0fe0f35e0d5c4793a84f8c4945067ca6 [file] [log] [blame]
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00200000
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]4CONFIG_SPL_GPIO_SUPPORT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
6CONFIG_SPL_LIBGENERIC_SUPPORT=y
7CONFIG_SYS_MALLOC_F_LEN=0x4000
8CONFIG_ROCKCHIP_RK3399=y
Philipp Tomsich7427c392017-11-24 14:44:59 +0100[diff] [blame]9CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]10CONFIG_TARGET_PUMA_RK3399=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]11CONFIG_NR_DRAM_BANKS=1
12CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]13CONFIG_DEBUG_UART_BASE=0xFF180000
14CONFIG_DEBUG_UART_CLOCK=24000000
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]15CONFIG_SPL_SPI_FLASH_SUPPORT=y
16CONFIG_SPL_SPI_SUPPORT=y
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]17CONFIG_DEBUG_UART=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]18CONFIG_FIT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]19CONFIG_SPL_LOAD_FIT=y
Philipp Tomsich9eefd0f2017-05-05 19:22:54 +0200[diff] [blame]20CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]21CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]22CONFIG_MISC_INIT_R=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]23# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]24CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Goldschmidtcc4078c2018-09-30 14:31:53 +0200[diff] [blame]25CONFIG_SPL_TEXT_BASE=0xff8c2000
Philipp Tomsicheade1642017-06-07 18:13:42 +0200[diff] [blame]26CONFIG_SPL_BOARD_INIT=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]27# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
28# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
29CONFIG_SPL_STACK_R=y
30CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
31CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]32CONFIG_SPL_I2C_SUPPORT=y
33CONFIG_SPL_POWER_SUPPORT=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]34CONFIG_SPL_SPI_LOAD=y
Philipp Tomsichf9413732017-09-13 21:29:42 +0200[diff] [blame]35CONFIG_SPL_ATF=y
Philipp Tomsich2e265192019-02-01 15:24:26 +0100[diff] [blame]36CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]37CONFIG_CMD_BOOTZ=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]38CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]39CONFIG_CMD_I2C=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]40CONFIG_CMD_MMC=y
41CONFIG_CMD_SF=y
42CONFIG_CMD_SPI=y
43CONFIG_CMD_USB=y
44# CONFIG_CMD_SETEXPR is not set
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]45CONFIG_CMD_BMP=y
46CONFIG_CMD_CACHE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]47CONFIG_CMD_TIME=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]48CONFIG_CMD_PMIC=y
49CONFIG_CMD_REGULATOR=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]50CONFIG_SPL_OF_CONTROL=y
Philipp Tomsich00fd83f2017-09-12 17:32:29 +0200[diff] [blame]51CONFIG_OF_LIVE=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]52CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600"
Philipp Tomsich57806cb2017-05-31 18:18:50 +0200[diff] [blame]53CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]54CONFIG_ENV_IS_IN_MMC=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]55CONFIG_REGMAP=y
56CONFIG_SPL_REGMAP=y
57CONFIG_SYSCON=y
58CONFIG_SPL_SYSCON=y
59CONFIG_CLK=y
60CONFIG_SPL_CLK=y
61CONFIG_ROCKCHIP_GPIO=y
Philipp Tomsicha4dbfc32017-05-31 18:18:49 +0200[diff] [blame]62CONFIG_SYS_I2C_ROCKCHIP=y
Philipp Tomsichf781e802017-05-05 19:21:41 +0200[diff] [blame]63CONFIG_MISC=y
64CONFIG_ROCKCHIP_EFUSE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]65CONFIG_MMC_DW=y
66CONFIG_MMC_DW_ROCKCHIP=y
67CONFIG_MMC_SDHCI=y
Philipp Tomsichdf23b0d2018-03-26 19:59:08 +0200[diff] [blame]68CONFIG_MMC_SDHCI_SDMA=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]69CONFIG_MMC_SDHCI_ROCKCHIP=y
70CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]71CONFIG_SF_DEFAULT_SPEED=20000000
Philipp Tomsichb1c07ff2019-02-03 15:59:23 +0100[diff] [blame]72CONFIG_SPI_FLASH_GIGADEVICE=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]73CONFIG_SPI_FLASH_WINBOND=y
74CONFIG_PHY_MICREL=y
Philipp Tomsich87321152017-10-30 14:44:55 +0100[diff] [blame]75CONFIG_PHY_MICREL_KSZ90X1=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]76CONFIG_DM_ETH=y
77CONFIG_ETH_DESIGNWARE=y
78CONFIG_GMAC_ROCKCHIP=y
79CONFIG_PINCTRL=y
80CONFIG_SPL_PINCTRL=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]81CONFIG_DM_PMIC=y
Philipp Tomsich3baf4402018-11-30 20:00:09 +0100[diff] [blame]82CONFIG_DM_PMIC_FAN53555=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]83CONFIG_PMIC_RK8XX=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]84CONFIG_SPL_DM_REGULATOR=y
Christoph Muellner8356c892019-01-02 15:09:17 +0100[diff] [blame]85CONFIG_REGULATOR_PWM=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]86CONFIG_DM_REGULATOR_FIXED=y
Philipp Tomsich070aba92017-09-29 19:28:03 +0200[diff] [blame]87CONFIG_SPL_DM_REGULATOR_FIXED=y
88CONFIG_DM_REGULATOR_GPIO=y
Philipp Tomsich222464f2017-05-31 18:18:46 +0200[diff] [blame]89CONFIG_REGULATOR_RK8XX=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]90CONFIG_PWM_ROCKCHIP=y
91CONFIG_RAM=y
92CONFIG_SPL_RAM=y
Klaus Gogercda97be2018-04-13 10:54:28 +0200[diff] [blame]93CONFIG_DM_RTC=y
94CONFIG_RTC_ISL1208=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]95CONFIG_DEBUG_UART_SHIFT=2
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]96CONFIG_ROCKCHIP_SPI=y
97CONFIG_SYSRESET=y
98CONFIG_USB=y
99CONFIG_USB_XHCI_HCD=y
100CONFIG_USB_XHCI_DWC3=y
101CONFIG_USB_EHCI_HCD=y
102CONFIG_USB_EHCI_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]103CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]104CONFIG_USB_ETHER_ASIX=y
105CONFIG_USB_ETHER_ASIX88179=y
106CONFIG_USB_ETHER_MCS7830=y
107CONFIG_USB_ETHER_RTL8152=y
108CONFIG_USB_ETHER_SMSC95XX=y
Philipp Tomsich8e530f22017-06-06 09:15:15 +0200[diff] [blame]109CONFIG_DM_VIDEO=y
110CONFIG_DISPLAY=y
111CONFIG_VIDEO_ROCKCHIP=y
112CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Philipp Tomsich23aec1d2017-03-28 18:48:52 +0200[diff] [blame]113CONFIG_ERRNO_STR=y