Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 1ea9789 | 2020-05-10 11:40:00 -0600 | [diff] [blame] | 7 | #include <bootstage.h> |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 8 | #include <dm.h> |
| 9 | #include <errno.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 11 | #include <timer.h> |
| 12 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 13 | #include <linux/bitops.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 14 | #include <linux/err.h> |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 15 | |
| 16 | #define CNT_CNTRL_RESET BIT(4) |
| 17 | |
| 18 | struct cadence_ttc_regs { |
| 19 | u32 clk_cntrl1; /* 0x0 - Clock Control 1 */ |
| 20 | u32 clk_cntrl2; /* 0x4 - Clock Control 2 */ |
| 21 | u32 clk_cntrl3; /* 0x8 - Clock Control 3 */ |
| 22 | u32 counter_cntrl1; /* 0xC - Counter Control 1 */ |
| 23 | u32 counter_cntrl2; /* 0x10 - Counter Control 2 */ |
| 24 | u32 counter_cntrl3; /* 0x14 - Counter Control 3 */ |
| 25 | u32 counter_val1; /* 0x18 - Counter Control 1 */ |
| 26 | u32 counter_val2; /* 0x1C - Counter Control 2 */ |
| 27 | u32 counter_val3; /* 0x20 - Counter Control 3 */ |
| 28 | u32 reserved[15]; |
| 29 | u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */ |
| 30 | u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */ |
| 31 | u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */ |
| 32 | }; |
| 33 | |
| 34 | struct cadence_ttc_priv { |
| 35 | struct cadence_ttc_regs *regs; |
| 36 | }; |
| 37 | |
Michal Simek | 8e434fc | 2018-04-18 14:03:56 +0200 | [diff] [blame] | 38 | #if CONFIG_IS_ENABLED(BOOTSTAGE) |
| 39 | ulong timer_get_boot_us(void) |
| 40 | { |
| 41 | u64 ticks = 0; |
| 42 | u32 rate = 1; |
| 43 | u64 us; |
| 44 | int ret; |
| 45 | |
| 46 | ret = dm_timer_init(); |
| 47 | if (!ret) { |
| 48 | /* The timer is available */ |
| 49 | rate = timer_get_rate(gd->timer); |
| 50 | timer_get_count(gd->timer, &ticks); |
| 51 | } else { |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | us = (ticks * 1000) / rate; |
| 56 | return us; |
| 57 | } |
| 58 | #endif |
| 59 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 60 | static u64 cadence_ttc_get_count(struct udevice *dev) |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 61 | { |
| 62 | struct cadence_ttc_priv *priv = dev_get_priv(dev); |
| 63 | |
Sean Anderson | 947fc2d | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 64 | return readl(&priv->regs->counter_val1); |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | static int cadence_ttc_probe(struct udevice *dev) |
| 68 | { |
| 69 | struct cadence_ttc_priv *priv = dev_get_priv(dev); |
| 70 | |
| 71 | /* Disable interrupts for sure */ |
| 72 | writel(0, &priv->regs->interrupt_enable1); |
| 73 | writel(0, &priv->regs->interrupt_enable2); |
| 74 | writel(0, &priv->regs->interrupt_enable3); |
| 75 | |
| 76 | /* Make sure that clocks are configured properly without prescaller */ |
| 77 | writel(0, &priv->regs->clk_cntrl1); |
| 78 | writel(0, &priv->regs->clk_cntrl2); |
| 79 | writel(0, &priv->regs->clk_cntrl3); |
| 80 | |
| 81 | /* Reset and enable this counter */ |
| 82 | writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1); |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 87 | static int cadence_ttc_of_to_plat(struct udevice *dev) |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 88 | { |
| 89 | struct cadence_ttc_priv *priv = dev_get_priv(dev); |
| 90 | |
Michal Simek | 6138cd1 | 2018-05-16 10:56:09 +0200 | [diff] [blame] | 91 | priv->regs = map_physmem(dev_read_addr(dev), |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 92 | sizeof(struct cadence_ttc_regs), MAP_NOCACHE); |
Michal Simek | 6138cd1 | 2018-05-16 10:56:09 +0200 | [diff] [blame] | 93 | if (IS_ERR(priv->regs)) |
| 94 | return PTR_ERR(priv->regs); |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static const struct timer_ops cadence_ttc_ops = { |
| 100 | .get_count = cadence_ttc_get_count, |
| 101 | }; |
| 102 | |
| 103 | static const struct udevice_id cadence_ttc_ids[] = { |
| 104 | { .compatible = "cdns,ttc" }, |
| 105 | {} |
| 106 | }; |
| 107 | |
| 108 | U_BOOT_DRIVER(cadence_ttc) = { |
| 109 | .name = "cadence_ttc", |
| 110 | .id = UCLASS_TIMER, |
| 111 | .of_match = cadence_ttc_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 112 | .of_to_plat = cadence_ttc_of_to_plat, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 113 | .priv_auto = sizeof(struct cadence_ttc_priv), |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 114 | .probe = cadence_ttc_probe, |
| 115 | .ops = &cadence_ttc_ops, |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 116 | }; |