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Michal Simek0dd222b2013-04-22 14:56:49 +02001/*
Michal Simek9ecd2682015-11-30 16:13:03 +01002 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek0dd222b2013-04-22 14:56:49 +02003 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02007 */
8
9#include <common.h>
Michal Simek9ecd2682015-11-30 16:13:03 +010010#include <dm.h>
Michal Simekc57ba042014-02-24 11:16:31 +010011#include <fdtdec.h>
12#include <libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020013#include <malloc.h>
14#include <sdhci.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020015
Siva Durga Prasad Paladuguf02a5e22016-01-05 12:21:04 +053016#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
17# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
18#endif
19
Simon Glass4cc87fb2016-07-05 17:10:15 -060020struct arasan_sdhci_plat {
21 struct mmc_config cfg;
22 struct mmc mmc;
23};
24
Michal Simek9ecd2682015-11-30 16:13:03 +010025static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek0dd222b2013-04-22 14:56:49 +020026{
Simon Glass4cc87fb2016-07-05 17:10:15 -060027 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010028 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
29 struct sdhci_host *host = dev_get_priv(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -060030 int ret;
Michal Simek0dd222b2013-04-22 14:56:49 +020031
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +053032 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +010033 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +053034
35#ifdef CONFIG_ZYNQ_HISPD_BROKEN
36 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
37#endif
38
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +010039 host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
40
41 ret = sdhci_setup_cfg(&plat->cfg, host, 0,
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +090042 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass4cc87fb2016-07-05 17:10:15 -060043 host->mmc = &plat->mmc;
44 if (ret)
45 return ret;
46 host->mmc->priv = host;
Simon Glass77ca42b2016-05-01 13:52:34 -060047 host->mmc->dev = dev;
Simon Glass4cc87fb2016-07-05 17:10:15 -060048 upriv->mmc = host->mmc;
Michal Simek9ecd2682015-11-30 16:13:03 +010049
Simon Glass4cc87fb2016-07-05 17:10:15 -060050 return sdhci_probe(dev);
Michal Simek0dd222b2013-04-22 14:56:49 +020051}
Michal Simek9ecd2682015-11-30 16:13:03 +010052
53static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
54{
55 struct sdhci_host *host = dev_get_priv(dev);
56
Masahiro Yamadaa4405612016-04-22 20:59:31 +090057 host->name = dev->name;
Michal Simek9ecd2682015-11-30 16:13:03 +010058 host->ioaddr = (void *)dev_get_addr(dev);
59
60 return 0;
61}
62
Simon Glass4cc87fb2016-07-05 17:10:15 -060063static int arasan_sdhci_bind(struct udevice *dev)
64{
65 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -060066
Masahiro Yamadacdb67f32016-09-06 22:17:32 +090067 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass4cc87fb2016-07-05 17:10:15 -060068}
69
Michal Simek9ecd2682015-11-30 16:13:03 +010070static const struct udevice_id arasan_sdhci_ids[] = {
71 { .compatible = "arasan,sdhci-8.9a" },
72 { }
73};
74
75U_BOOT_DRIVER(arasan_sdhci_drv) = {
76 .name = "arasan_sdhci",
77 .id = UCLASS_MMC,
78 .of_match = arasan_sdhci_ids,
79 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass4cc87fb2016-07-05 17:10:15 -060080 .ops = &sdhci_ops,
81 .bind = arasan_sdhci_bind,
Michal Simek9ecd2682015-11-30 16:13:03 +010082 .probe = arasan_sdhci_probe,
83 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass4cc87fb2016-07-05 17:10:15 -060084 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simek9ecd2682015-11-30 16:13:03 +010085};