blob: 25f8c978c6d155862f244b2e80bf20ce1f61e92e [file] [log] [blame]
Hou Zhiqiang7c3f83d2019-08-20 09:35:24 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T2080RDB Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
Camelia Groza621bd512021-04-13 19:47:56 +03006 * Copyright 2019-2021 NXP
Hou Zhiqiang7c3f83d2019-08-20 09:35:24 +00007 */
8
9/include/ "t2080.dtsi"
10
11/ {
12 model = "fsl,T2080RDB";
13 compatible = "fsl,T2080RDB";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
Xiaowei Bao258f3692020-06-04 23:16:58 +080017
18 aliases {
19 spi0 = &espi0;
20 };
21};
22
Camelia Groza621bd512021-04-13 19:47:56 +030023&soc {
24 fman@400000 {
25 ethernet@e0000 {
26 phy-handle = <&xg_aq1202_phy3>;
27 phy-connection-type = "xgmii";
28 };
29
30 ethernet@e2000 {
31 phy-handle = <&xg_aq1202_phy4>;
32 phy-connection-type = "xgmii";
33 };
34
35 ethernet@e4000 {
36 phy-handle = <&rgmii_phy1>;
37 phy-connection-type = "rgmii";
38 };
39
40 ethernet@e6000 {
41 phy-handle = <&rgmii_phy2>;
42 phy-connection-type = "rgmii";
43 };
44
45 ethernet@f0000 {
46 phy-handle = <&xg_cs4315_phy2>;
47 phy-connection-type = "xgmii";
48 };
49
50 ethernet@f2000 {
51 phy-handle = <&xg_cs4315_phy1>;
52 phy-connection-type = "xgmii";
53 };
54
55 mdio@fc000 {
56 rgmii_phy1: ethernet-phy@1 {
57 reg = <0x1>;
58 };
59 rgmii_phy2: ethernet-phy@2 {
60 reg = <0x2>;
61 };
62 };
63
64 mdio@fd000 {
65 xg_cs4315_phy1: ethernet-phy@c {
66 compatible = "ethernet-phy-id13e5.1002";
67 reg = <0xc>;
68 };
69
70 xg_cs4315_phy2: ethernet-phy@d {
71 compatible = "ethernet-phy-id13e5.1002";
72 reg = <0xd>;
73 };
74
75 xg_aq1202_phy3: ethernet-phy@0 {
76 compatible = "ethernet-phy-ieee802.3-c45";
77 reg = <0x0>;
78 };
79
80 xg_aq1202_phy4: ethernet-phy@1 {
81 compatible = "ethernet-phy-ieee802.3-c45";
82 reg = <0x1>;
83 };
84 };
85 };
86};
87
Xiaowei Bao258f3692020-06-04 23:16:58 +080088&espi0 {
89 status = "okay";
90 flash@0 {
91 compatible = "jedec,spi-nor"; /* 16MB */
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0>;
95 spi-max-frequency = <10000000>; /* input clock */
96 };
Hou Zhiqiang7c3f83d2019-08-20 09:35:24 +000097};
Chris Packham92790a52021-03-03 14:09:45 +130098
99&i2c0 {
100 status = "okay";
101 rtc@68 {
102 compatible = "dallas,ds1339";
103 reg = <0x68>;
104 };
105};
Camelia Groza621bd512021-04-13 19:47:56 +0300106
107/include/ "t2080si-post.dtsi"