blob: 76ba0ea1675ecc95fd33f5dc40f453ccf2827ae5 [file] [log] [blame]
Philippe Reynes697f15e2018-10-11 18:31:58 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
4 */
5
6#include "skeleton64.dtsi"
7
8/ {
9 compatible = "brcm,bcm6858";
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 cpus {
14 #address-cells = <2>;
15 #size-cells = <0>;
16 u-boot,dm-pre-reloc;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a53", "arm,armv8";
20 device_type = "cpu";
21 reg = <0x0 0x0>;
22 next-level-cache = <&l2>;
23 u-boot,dm-pre-reloc;
24 };
25
26 cpu1: cpu@1 {
27 compatible = "arm,cortex-a53", "arm,armv8";
28 device_type = "cpu";
29 reg = <0x0 0x1>;
30 next-level-cache = <&l2>;
31 u-boot,dm-pre-reloc;
32 };
33
34 cpu2: cpu@2 {
35 compatible = "arm,cortex-a53", "arm,armv8";
36 device_type = "cpu";
37 reg = <0x0 0x2>;
38 next-level-cache = <&l2>;
39 u-boot,dm-pre-reloc;
40 };
41
42 cpu3: cpu@3 {
43 compatible = "arm,cortex-a53", "arm,armv8";
44 device_type = "cpu";
45 reg = <0x0 0x3>;
46 next-level-cache = <&l2>;
47 u-boot,dm-pre-reloc;
48 };
49
50 l2: l2-cache0 {
51 compatible = "cache";
52 u-boot,dm-pre-reloc;
53 };
54 };
55
56 clocks {
57 compatible = "simple-bus";
58 #address-cells = <2>;
59 #size-cells = <2>;
60 ranges;
61 u-boot,dm-pre-reloc;
62
63 periph_osc: periph-osc {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <200000000>;
67 u-boot,dm-pre-reloc;
68 };
69 };
70
71 ubus {
72 compatible = "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <2>;
75 u-boot,dm-pre-reloc;
76
77 uart0: serial@ff800640 {
Álvaro Fernández Rojas4ab29872018-12-01 18:42:09 +010078 compatible = "brcm,bcm6345-uart";
Philippe Reynes697f15e2018-10-11 18:31:58 +020079 reg = <0x0 0xff800640 0x0 0x18>;
80 clocks = <&periph_osc>;
81
82 status = "disabled";
83 };
Philippe Reynese0ed3fc2019-01-28 15:37:30 +010084
Philippe Reynes61c6b162019-03-22 17:02:02 +010085 leds: led-controller@ff800800 {
86 compatible = "brcm,bcm6858-leds";
87 reg = <0x0 0xff800800 0x0 0xe4>;
88
89 status = "disabled";
90 };
91
Philippe Reynese0ed3fc2019-01-28 15:37:30 +010092 wdt1: watchdog@ff802780 {
93 compatible = "brcm,bcm6345-wdt";
94 reg = <0x0 0xff802780 0x0 0x14>;
95 clocks = <&periph_osc>;
96 };
97
98 wdt2: watchdog@ff8027c0 {
99 compatible = "brcm,bcm6345-wdt";
100 reg = <0x0 0xff8027c0 0x0 0x14>;
101 clocks = <&periph_osc>;
102 };
103
104 wdt-reboot {
105 compatible = "wdt-reboot";
106 wdt = <&wdt1>;
107 };
Philippe Reynesc0200c12019-03-07 11:36:37 +0100108
109 gpio0: gpio-controller@0xff800500 {
110 compatible = "brcm,bcm6345-gpio";
111 reg = <0x0 0xff800500 0x0 0x4>,
112 <0x0 0xff800520 0x0 0x4>;
113 gpio-controller;
114 #gpio-cells = <2>;
115
116 status = "disabled";
117 };
118
119 gpio1: gpio-controller@0xff800504 {
120 compatible = "brcm,bcm6345-gpio";
121 reg = <0x0 0xff800504 0x0 0x4>,
122 <0x0 0xff800524 0x0 0x4>;
123 gpio-controller;
124 #gpio-cells = <2>;
125
126 status = "disabled";
127 };
128
129 gpio2: gpio-controller@0xff800508 {
130 compatible = "brcm,bcm6345-gpio";
131 reg = <0x0 0xff800508 0x0 0x4>,
132 <0x0 0xff800528 0x0 0x4>;
133 gpio-controller;
134 #gpio-cells = <2>;
135
136 status = "disabled";
137 };
138
139 gpio3: gpio-controller@0xff80050c {
140 compatible = "brcm,bcm6345-gpio";
141 reg = <0x0 0xff80050c 0x0 0x4>,
142 <0x0 0xff80052c 0x0 0x4>;
143 gpio-controller;
144 #gpio-cells = <2>;
145
146 status = "disabled";
147 };
148
149 gpio4: gpio-controller@0xff800510 {
150 compatible = "brcm,bcm6345-gpio";
151 reg = <0x0 0xff800510 0x0 0x4>,
152 <0x0 0xff800530 0x0 0x4>;
153 gpio-controller;
154 #gpio-cells = <2>;
155
156 status = "disabled";
157 };
158
159 gpio5: gpio-controller@0xff800514 {
160 compatible = "brcm,bcm6345-gpio";
161 reg = <0x0 0xff800514 0x0 0x4>,
162 <0x0 0xff800534 0x0 0x4>;
163 gpio-controller;
164 #gpio-cells = <2>;
165
166 status = "disabled";
167 };
168
169 gpio6: gpio-controller@0xff800518 {
170 compatible = "brcm,bcm6345-gpio";
171 reg = <0x0 0xff800518 0x0 0x4>,
172 <0x0 0xff800538 0x0 0x4>;
173 gpio-controller;
174 #gpio-cells = <2>;
175
176 status = "disabled";
177 };
178
179 gpio7: gpio-controller@0xff80051c {
180 compatible = "brcm,bcm6345-gpio";
181 reg = <0x0 0xff80051c 0x0 0x4>,
182 <0x0 0xff80053c 0x0 0x4>;
183 gpio-controller;
184 #gpio-cells = <2>;
185
186 status = "disabled";
187 };
Philippe Reynesd80b0882019-03-15 15:14:42 +0100188
189 nand: nand-controller@ff801800 {
190 compatible = "brcm,nand-bcm6858",
191 "brcm,brcmnand-v5.0",
192 "brcm,brcmnand";
193 reg-names = "nand", "nand-int-base", "nand-cache";
194 reg = <0x0 0xff801800 0x0 0x180>,
195 <0x0 0xff802000 0x0 0x10>,
196 <0x0 0xff801c00 0x0 0x200>;
197 parameter-page-big-endian = <0>;
198
199 status = "disabled";
200 };
Philippe Reynes697f15e2018-10-11 18:31:58 +0200201 };
202};