| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Device Tree file for Marvell RD-AXPWiFiAP. |
| 4 | * |
| 5 | * Note: this board is shipped with a new generation boot loader that |
| 6 | * remaps internal registers at 0xf1000000. Therefore, if earlyprintk |
| 7 | * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the |
| 8 | * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. |
| 9 | * |
| 10 | * Copyright (C) 2013 Marvell |
| 11 | * |
| 12 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 13 | */ |
| 14 | |
| 15 | /dts-v1/; |
| 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> |
| 18 | #include "armada-xp-mv78230.dtsi" |
| 19 | |
| 20 | / { |
| 21 | model = "Marvell RD-AXPWiFiAP"; |
| 22 | compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; |
| 23 | |
| 24 | chosen { |
| 25 | stdout-path = "serial0:115200n8"; |
| 26 | }; |
| 27 | |
| 28 | memory@0 { |
| 29 | device_type = "memory"; |
| 30 | reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ |
| 31 | }; |
| 32 | |
| 33 | soc { |
| 34 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
| 35 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 36 | MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 |
| 37 | MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; |
| 38 | |
| 39 | internal-regs { |
| 40 | /* UART0 */ |
| 41 | serial@12000 { |
| 42 | status = "okay"; |
| 43 | }; |
| 44 | |
| 45 | /* UART1 */ |
| 46 | serial@12100 { |
| 47 | status = "okay"; |
| 48 | }; |
| 49 | |
| 50 | sata@a0000 { |
| 51 | nr-ports = <1>; |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
| 55 | ethernet@70000 { |
| 56 | pinctrl-0 = <&ge0_rgmii_pins>; |
| 57 | pinctrl-names = "default"; |
| 58 | status = "okay"; |
| 59 | phy = <&phy0>; |
| 60 | phy-mode = "rgmii-id"; |
| 61 | }; |
| 62 | ethernet@74000 { |
| 63 | pinctrl-0 = <&ge1_rgmii_pins>; |
| 64 | pinctrl-names = "default"; |
| 65 | status = "okay"; |
| 66 | phy = <&phy1>; |
| 67 | phy-mode = "rgmii-id"; |
| 68 | }; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | gpio-keys { |
| 73 | compatible = "gpio-keys"; |
| 74 | pinctrl-0 = <&keys_pin>; |
| 75 | pinctrl-names = "default"; |
| 76 | |
| 77 | button-reset { |
| 78 | label = "Factory Reset Button"; |
| 79 | linux,code = <KEY_SETUP>; |
| 80 | gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| 81 | }; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | &mdio { |
| 86 | phy0: ethernet-phy@0 { |
| 87 | reg = <0>; |
| 88 | }; |
| 89 | |
| 90 | phy1: ethernet-phy@1 { |
| 91 | reg = <1>; |
| 92 | }; |
| 93 | }; |
| 94 | |
| 95 | &pciec { |
| 96 | status = "okay"; |
| 97 | |
| 98 | /* First mini-PCIe port */ |
| 99 | pcie@1,0 { |
| 100 | /* Port 0, Lane 0 */ |
| 101 | status = "okay"; |
| 102 | }; |
| 103 | |
| 104 | /* Second mini-PCIe port */ |
| 105 | pcie@2,0 { |
| 106 | /* Port 0, Lane 1 */ |
| 107 | status = "okay"; |
| 108 | }; |
| 109 | |
| 110 | /* Renesas uPD720202 USB 3.0 controller */ |
| 111 | pcie@3,0 { |
| 112 | /* Port 0, Lane 3 */ |
| 113 | status = "okay"; |
| 114 | }; |
| 115 | }; |
| 116 | |
| 117 | &pinctrl { |
| 118 | pinctrl-0 = <&phy_int_pin>; |
| 119 | pinctrl-names = "default"; |
| 120 | |
| 121 | keys_pin: keys-pin { |
| 122 | marvell,pins = "mpp33"; |
| 123 | marvell,function = "gpio"; |
| 124 | }; |
| 125 | |
| 126 | phy_int_pin: phy-int-pin { |
| 127 | marvell,pins = "mpp32"; |
| 128 | marvell,function = "gpio"; |
| 129 | }; |
| 130 | }; |
| 131 | |
| 132 | &spi0 { |
| 133 | status = "okay"; |
| 134 | |
| 135 | flash@0 { |
| 136 | #address-cells = <1>; |
| 137 | #size-cells = <1>; |
| 138 | compatible = "n25q128a13", "jedec,spi-nor"; |
| 139 | reg = <0>; /* Chip select 0 */ |
| 140 | spi-max-frequency = <108000000>; |
| 141 | }; |
| 142 | }; |