| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Device Tree file for Marvell Armada 395 GP board |
| 4 | * |
| 5 | * Copyright (C) 2016 Marvell |
| 6 | * |
| 7 | * Grzegorz Jaszczyk <jaz@semihalf.com> |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | #include "armada-395.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "Marvell Armada 395 GP Board"; |
| 15 | compatible = "marvell,a395-gp", "marvell,armada395", |
| 16 | "marvell,armada390"; |
| 17 | |
| 18 | chosen { |
| 19 | stdout-path = "serial0:115200n8"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | device_type = "memory"; |
| 24 | reg = <0x00000000 0x40000000>; /* 1 GB */ |
| 25 | }; |
| 26 | |
| 27 | soc { |
| 28 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
| 29 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; |
| 30 | |
| 31 | internal-regs { |
| 32 | i2c@11000 { |
| 33 | status = "okay"; |
| 34 | clock-frequency = <100000>; |
| 35 | |
| 36 | eeprom@57 { |
| 37 | compatible = "atmel,24c64"; |
| 38 | reg = <0x57>; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | serial@12000 { |
| 43 | /* |
| 44 | * Exported on the micro USB connector CON17 |
| 45 | * through an FTDI |
| 46 | */ |
| 47 | status = "okay"; |
| 48 | }; |
| 49 | |
| 50 | /* CON1 */ |
| 51 | usb@58000 { |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
| 55 | /* CON2 */ |
| 56 | sata@a8000 { |
| 57 | status = "okay"; |
| 58 | }; |
| 59 | |
| 60 | /* CON18 */ |
| 61 | sdhci@d8000 { |
| 62 | clock-frequency = <200000000>; |
| 63 | broken-cd; |
| 64 | wp-inverted; |
| 65 | bus-width = <8>; |
| 66 | status = "okay"; |
| 67 | no-1-8-v; |
| 68 | }; |
| 69 | |
| 70 | /* CON4 */ |
| 71 | usb3@f0000 { |
| 72 | status = "okay"; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | pcie { |
| 77 | status = "okay"; |
| 78 | |
| 79 | /* |
| 80 | * The two PCIe units are accessible through |
| 81 | * mini PCIe slot on the board. |
| 82 | */ |
| 83 | |
| 84 | /* CON7 */ |
| 85 | pcie@2,0 { |
| 86 | /* Port 1, Lane 0 */ |
| 87 | status = "okay"; |
| 88 | }; |
| 89 | |
| 90 | /* CON8 */ |
| 91 | pcie@4,0 { |
| 92 | /* Port 3, Lane 0 */ |
| 93 | status = "okay"; |
| 94 | }; |
| 95 | }; |
| 96 | }; |
| 97 | }; |
| 98 | |
| 99 | &nand_controller { |
| 100 | status = "okay"; |
| 101 | pinctrl-0 = <&nand_pins>; |
| 102 | pinctrl-names = "default"; |
| 103 | |
| 104 | nand@0 { |
| 105 | reg = <0>; |
| 106 | label = "pxa3xx_nand-0"; |
| 107 | nand-rb = <0>; |
| 108 | marvell,nand-keep-config; |
| 109 | nand-on-flash-bbt; |
| 110 | nand-ecc-strength = <4>; |
| 111 | nand-ecc-step-size = <512>; |
| 112 | |
| 113 | partitions { |
| 114 | compatible = "fixed-partitions"; |
| 115 | #address-cells = <1>; |
| 116 | #size-cells = <1>; |
| 117 | |
| 118 | partition@0 { |
| 119 | label = "U-Boot"; |
| 120 | reg = <0x00000000 0x00600000>; |
| 121 | read-only; |
| 122 | }; |
| 123 | |
| 124 | partition@800000 { |
| 125 | label = "uImage"; |
| 126 | reg = <0x00600000 0x00400000>; |
| 127 | read-only; |
| 128 | }; |
| 129 | |
| 130 | partition@1000000 { |
| 131 | label = "Root"; |
| 132 | reg = <0x00a00000 0x3f600000>; |
| 133 | }; |
| 134 | }; |
| 135 | }; |
| 136 | }; |