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git01.mediatek.com / filogic / uboot / 6186a592463935d91ec9d7ec8d62de6ce80405b1 / . / dts / upstream / src / arm / marvell / armada-385-clearfog-gtr-l8.dts
blob: cb85f8e31dfc501ea57759949009a2b337ad72f2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3#include "armada-385-clearfog-gtr.dtsi"
4
5/ {
6 model = "SolidRun Clearfog GTR L8";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
8 "marvell,armada380";
9
10 /* CON25 */
11 sfp1: sfp-1 {
12 compatible = "sff,sfp";
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
18 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]19};
20
21&mdio {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]22 switch0: ethernet-switch@4 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]23 compatible = "marvell,mv88e6190";
24 reg = <4>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
27 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
28
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]29 ethernet-ports {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]30 #address-cells = <1>;
31 #size-cells = <0>;
32
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]33 ethernet-port@1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]34 reg = <1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]35 label = "lan1";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]36 phy-handle = <&switch0phy0>;
37 };
38
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]39 ethernet-port@2 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]40 reg = <2>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]41 label = "lan2";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]42 phy-handle = <&switch0phy1>;
43 };
44
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]45 ethernet-port@3 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]46 reg = <3>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]47 label = "lan3";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]48 phy-handle = <&switch0phy2>;
49 };
50
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]51 ethernet-port@4 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]52 reg = <4>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]53 label = "lan4";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]54 phy-handle = <&switch0phy3>;
55 };
56
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]57 ethernet-port@5 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]58 reg = <5>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]59 label = "lan5";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]60 phy-handle = <&switch0phy4>;
61 };
62
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]63 ethernet-port@6 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]64 reg = <6>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]65 label = "lan6";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]66 phy-handle = <&switch0phy5>;
67 };
68
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]69 ethernet-port@7 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]70 reg = <7>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]71 label = "lan7";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]72 phy-handle = <&switch0phy6>;
73 };
74
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]75 ethernet-port@8 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]76 reg = <8>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]77 label = "lan8";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]78 phy-handle = <&switch0phy7>;
79 };
80
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]81 ethernet-port@9 {
82 reg = <9>;
83 label = "lan-sfp";
84 phy-mode = "sgmii";
85 sfp = <&sfp1>;
86 managed = "in-band-status";
87 };
88
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]89 ethernet-port@10 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]90 reg = <10>;
91 phy-mode = "2500base-x";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]92 ethernet = <&eth1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]93
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]94 fixed-link {
95 speed = <2500>;
96 full-duplex;
97 };
98 };
99
100 };
101
102 mdio {
103 #address-cells = <1>;
104 #size-cells = <0>;
105
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]106 switch0phy0: ethernet-phy@1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]107 reg = <0x1>;
108 };
109
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]110 switch0phy1: ethernet-phy@2 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]111 reg = <0x2>;
112 };
113
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]114 switch0phy2: ethernet-phy@3 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]115 reg = <0x3>;
116 };
117
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]118 switch0phy3: ethernet-phy@4 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]119 reg = <0x4>;
120 };
121
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]122 switch0phy4: ethernet-phy@5 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]123 reg = <0x5>;
124 };
125
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]126 switch0phy5: ethernet-phy@6 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]127 reg = <0x6>;
128 };
129
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]130 switch0phy6: ethernet-phy@7 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]131 reg = <0x7>;
132 };
133
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]134 switch0phy7: ethernet-phy@8 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]135 reg = <0x8>;
136 };
137 };
138
139 };
140};