Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 1 | /* |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 2 | modified from SH-IPL+g |
| 3 | Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. |
| 4 | |
Wolfgang Denk | 0a5c214 | 2007-12-27 01:52:50 +0100 | [diff] [blame] | 5 | Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R |
| 6 | |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 7 | Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> |
| 8 | |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <version.h> |
| 14 | |
| 15 | #include <asm/processor.h> |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 16 | #include <asm/macro.h> |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 17 | |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 18 | #ifdef CONFIG_CPU_SH7751 |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 19 | #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ |
| 20 | #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 21 | #ifdef CONFIG_MARUBUN_PCCARD |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 22 | #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 |
| 23 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 24 | #else /* CONFIG_MARUBUN_PCCARD */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 25 | #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 |
| 26 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 27 | #endif /* CONFIG_MARUBUN_PCCARD */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 28 | #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 |
| 29 | A2: 1-3 A1: 1-3 A0: 0-1 */ |
| 30 | #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ |
| 31 | #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ |
| 32 | #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ |
| 33 | #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 34 | #else /* CONFIG_CPU_SH7751 */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 35 | #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ |
| 36 | #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ |
| 37 | #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 |
| 38 | A3:2 A2:15 A1:15 A0:15 A0B:7 */ |
| 39 | #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 |
| 40 | A2: 1-3 A1: 1-3 A0: 0-1 */ |
| 41 | #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ |
| 42 | #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ |
| 43 | #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ |
| 44 | #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 45 | #endif /* CONFIG_CPU_SH7751 */ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 46 | |
| 47 | .global lowlevel_init |
| 48 | .text |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 49 | .align 2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 50 | |
| 51 | lowlevel_init: |
| 52 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 53 | write32 CCR_A, CCR_D_DISABLE |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 54 | |
| 55 | init_bsc: |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 56 | write16 FRQCR_A, FRQCR_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 57 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 58 | write32 BCR1_A, BCR1_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 59 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 60 | write16 BCR2_A, BCR2_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 61 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 62 | write32 WCR1_A, WCR1_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 63 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 64 | write32 WCR2_A, WCR2_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 65 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 66 | write32 WCR3_A, WCR3_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 67 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 68 | write32 MCR_A, MCR_D1 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 69 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 70 | /* Set SDRAM mode */ |
Nobuhiro Iwamatsu | fcbff80 | 2009-01-11 17:48:56 +0900 | [diff] [blame] | 71 | write8 SDMR3_A, SDMR3_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 72 | |
Wolfgang Denk | 0a5c214 | 2007-12-27 01:52:50 +0100 | [diff] [blame] | 73 | ! Do you need PCMCIA setting? |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 74 | ! If so, please add the lines here... |
| 75 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 76 | write16 RTCNT_A, RTCNT_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 77 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 78 | write16 RTCOR_A, RTCOR_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 79 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 80 | write16 RTCSR_A, RTCSR_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 81 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 82 | write16 RFCR_A, RFCR_D |
| 83 | |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 84 | /* Wait DRAM refresh 30 times */ |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 85 | mov #30, r3 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 86 | 1: |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 87 | mov.w @r1, r0 |
| 88 | extu.w r0, r2 |
| 89 | cmp/hi r3, r2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 90 | bf 1b |
| 91 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 92 | write32 MCR_A, MCR_D2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 93 | |
Jean-Christophe PLAGNIOL-VILLARD | b9c2172 | 2008-12-20 19:29:49 +0100 | [diff] [blame] | 94 | /* Set SDRAM mode */ |
Nobuhiro Iwamatsu | fcbff80 | 2009-01-11 17:48:56 +0900 | [diff] [blame] | 95 | write8 SDMR3_A, SDMR3_D |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 96 | |
| 97 | rts |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 98 | nop |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 99 | |
| 100 | .align 2 |
| 101 | |
Jean-Christophe PLAGNIOL-VILLARD | bd96370 | 2008-12-20 19:29:48 +0100 | [diff] [blame] | 102 | CCR_A: .long CCR |
| 103 | CCR_D_DISABLE: .long 0x0808 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 104 | FRQCR_A: .long FRQCR |
| 105 | FRQCR_D: |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 106 | #ifdef CONFIG_CPU_TYPE_R |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 107 | .word 0x0e1a /* 12:3:3 */ |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 108 | #else /* CONFIG_CPU_TYPE_R */ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 109 | #ifdef CONFIG_GOOD_SESH4 |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 110 | .word 0x00e13 /* 6:2:1 */ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 111 | #else |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 112 | .word 0x00e23 /* 6:1:1 */ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 113 | #endif |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 114 | .align 2 |
Nobuhiro Iwamatsu | f252745 | 2007-09-23 02:19:24 +0900 | [diff] [blame] | 115 | #endif /* CONFIG_CPU_TYPE_R */ |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 116 | |
| 117 | BCR1_A: .long BCR1 |
| 118 | BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ |
| 119 | BCR2_A: .long BCR2 |
| 120 | BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ |
| 121 | WCR1_A: .long WCR1 |
| 122 | WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ |
| 123 | WCR2_A: .long WCR2 |
| 124 | WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ |
| 125 | WCR3_A: .long WCR3 |
| 126 | WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ |
Wolfgang Denk | 0a5c214 | 2007-12-27 01:52:50 +0100 | [diff] [blame] | 127 | RTCSR_A: .long RTCSR |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 128 | RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ |
| 129 | .align 2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 130 | RTCNT_A: .long RTCNT |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 131 | RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ |
| 132 | .align 2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 133 | RTCOR_A: .long RTCOR |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 134 | RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ |
| 135 | .align 2 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 136 | SDMR3_A: .long SDMR3_ADDRESS |
Nobuhiro Iwamatsu | fcbff80 | 2009-01-11 17:48:56 +0900 | [diff] [blame] | 137 | SDMR3_D: .long 0x00 |
Nobuhiro Iwamatsu | 4525485 | 2007-05-13 21:01:03 +0900 | [diff] [blame] | 138 | MCR_A: .long MCR |
| 139 | MCR_D1: .long MCR_D1_VALUE |
| 140 | MCR_D2: .long MCR_D2_VALUE |
| 141 | RFCR_A: .long RFCR |
Nobuhiro Iwamatsu | 13650f1 | 2010-07-22 16:18:22 +0900 | [diff] [blame] | 142 | RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ |
| 143 | .align 2 |