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Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +09001/*
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09002 modified from SH-IPL+g
3 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
4
Wolfgang Denk0a5c2142007-12-27 01:52:50 +01005 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
6
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +09007 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
8
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090010*/
11
12#include <config.h>
13#include <version.h>
14
15#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010016#include <asm/macro.h>
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090017
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090018#ifdef CONFIG_CPU_SH7751
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010019#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
20#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090021#ifdef CONFIG_MARUBUN_PCCARD
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010022#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
23 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090024#else /* CONFIG_MARUBUN_PCCARD */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010025#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
26 A3:2 A2:15 A1:15 A0:6 A0B:7 */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090027#endif /* CONFIG_MARUBUN_PCCARD */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010028#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
29 A2: 1-3 A1: 1-3 A0: 0-1 */
30#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
31#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
32#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
33#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090034#else /* CONFIG_CPU_SH7751 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010035#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
36#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
37#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
38 A3:2 A2:15 A1:15 A0:15 A0B:7 */
39#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
40 A2: 1-3 A1: 1-3 A0: 0-1 */
41#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
42#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
43#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
44#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +090045#endif /* CONFIG_CPU_SH7751 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090046
47 .global lowlevel_init
48 .text
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010049 .align 2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090050
51lowlevel_init:
52
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010053 write32 CCR_A, CCR_D_DISABLE
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090054
55init_bsc:
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010056 write16 FRQCR_A, FRQCR_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090057
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010058 write32 BCR1_A, BCR1_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090059
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010060 write16 BCR2_A, BCR2_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090061
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010062 write32 WCR1_A, WCR1_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090063
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010064 write32 WCR2_A, WCR2_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090065
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010066 write32 WCR3_A, WCR3_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090067
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010068 write32 MCR_A, MCR_D1
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090069
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010070 /* Set SDRAM mode */
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +090071 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090072
Wolfgang Denk0a5c2142007-12-27 01:52:50 +010073 ! Do you need PCMCIA setting?
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090074 ! If so, please add the lines here...
75
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010076 write16 RTCNT_A, RTCNT_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090077
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010078 write16 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090079
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010080 write16 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090081
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010082 write16 RFCR_A, RFCR_D
83
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090084 /* Wait DRAM refresh 30 times */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010085 mov #30, r3
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900861:
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010087 mov.w @r1, r0
88 extu.w r0, r2
89 cmp/hi r3, r2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090090 bf 1b
91
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010092 write32 MCR_A, MCR_D2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090093
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +010094 /* Set SDRAM mode */
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +090095 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090096
97 rts
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +010098 nop
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +090099
100 .align 2
101
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100102CCR_A: .long CCR
103CCR_D_DISABLE: .long 0x0808
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900104FRQCR_A: .long FRQCR
105FRQCR_D:
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +0900106#ifdef CONFIG_CPU_TYPE_R
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900107 .word 0x0e1a /* 12:3:3 */
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +0900108#else /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900109#ifdef CONFIG_GOOD_SESH4
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900110 .word 0x00e13 /* 6:2:1 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900111#else
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900112 .word 0x00e23 /* 6:1:1 */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900113#endif
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900114.align 2
Nobuhiro Iwamatsuf2527452007-09-23 02:19:24 +0900115#endif /* CONFIG_CPU_TYPE_R */
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900116
117BCR1_A: .long BCR1
118BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
119BCR2_A: .long BCR2
120BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
121WCR1_A: .long WCR1
122WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
123WCR2_A: .long WCR2
124WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
125WCR3_A: .long WCR3
126WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100127RTCSR_A: .long RTCSR
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900128RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
129.align 2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900130RTCNT_A: .long RTCNT
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900131RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
132.align 2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900133RTCOR_A: .long RTCOR
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900134RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
135.align 2
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900136SDMR3_A: .long SDMR3_ADDRESS
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +0900137SDMR3_D: .long 0x00
Nobuhiro Iwamatsu45254852007-05-13 21:01:03 +0900138MCR_A: .long MCR
139MCR_D1: .long MCR_D1_VALUE
140MCR_D2: .long MCR_D2_VALUE
141RFCR_A: .long RFCR
Nobuhiro Iwamatsu13650f12010-07-22 16:18:22 +0900142RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
143.align 2