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git01.mediatek.com / filogic / uboot / 618212c156cba7fe3c947641708e1fb623a3f9ff / . / board / amcc / taishan / init.S
blob: ab1bb34fb87ced95dbbe60fe8cb1101c49c68ed0 [file] [log] [blame]
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]6 */
7
8#include <ppc_asm.tmpl>
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]9#include <asm/mmu.h>
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]10#include <config.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]11#include <asm/ppc4xx.h>
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]12
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]13/**************************************************************************
14 * TLB TABLE
15 *
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
19 *
20 * Pointer to the table is returned in r1
21 *
22 *************************************************************************/
23
24 .section .bootpg,"ax"
25 .globl tlbtab
26
27tlbtab:
28 tlbtab_start
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]29 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
30 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
31 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
32 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
33 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
34 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
Stefan Roese8d982302007-01-18 10:25:34 +0100[diff] [blame]35 tlbtab_end