| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_PX30_COMMON_H |
| 7 | #define __CONFIG_PX30_COMMON_H |
| 8 | |
| 9 | #include "rockchip-common.h" |
| 10 | |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 11 | /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ |
| Tom Rini | 3088b31 | 2022-12-04 10:04:13 -0500 | [diff] [blame] | 12 | #define CFG_IRAM_BASE 0xff020000 |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 13 | |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 14 | #define GICD_BASE 0xff131000 |
| 15 | #define GICC_BASE 0xff132000 |
| 16 | |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 17 | #define CFG_SYS_SDRAM_BASE 0 |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 18 | #define SDRAM_MAX_SIZE 0xff000000 |
| 19 | #define SDRAM_BANK_SIZE (2UL << 30) |
| 20 | |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 21 | #define ENV_MEM_LAYOUT_SETTINGS \ |
| 22 | "scriptaddr=0x00500000\0" \ |
| 23 | "pxefile_addr_r=0x00600000\0" \ |
| 24 | "fdt_addr_r=0x08300000\0" \ |
| 25 | "kernel_addr_r=0x00280000\0" \ |
| 26 | "kernel_addr_c=0x03e80000\0" \ |
| 27 | "ramdisk_addr_r=0x0a200000\0" |
| 28 | |
| 29 | #include <config_distro_bootcmd.h> |
| Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 30 | #define CFG_EXTRA_ENV_SETTINGS \ |
| Heiko Stuebner | aff82aa | 2019-07-16 22:17:13 +0200 | [diff] [blame] | 31 | ENV_MEM_LAYOUT_SETTINGS \ |
| 32 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| 33 | "partitions=" PARTS_DEFAULT \ |
| 34 | ROCKCHIP_DEVICE_SETTINGS \ |
| 35 | BOOTENV |
| 36 | |
| 37 | #endif |