| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2012 Atmel Corporation |
| 4 | * Copyright (C) 2019 Stefan Roese <sr@denx.de> |
| 5 | * |
| 6 | * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H__ |
| 10 | #define __CONFIG_H__ |
| 11 | |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 12 | #ifndef __ASSEMBLY__ |
| 13 | #include <linux/bitops.h> |
| 14 | #endif |
| 15 | |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 16 | /* ARM asynchronous clock */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 |
| 18 | #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 19 | |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 20 | /* SDRAM */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 21 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 22 | #define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 23 | |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 24 | /* NAND flash */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 25 | #define CFG_SYS_NAND_BASE 0x40000000 |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 26 | /* our ALE is AD21 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 27 | #define CFG_SYS_NAND_MASK_ALE BIT(21) |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 28 | /* our CLE is AD22 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 29 | #define CFG_SYS_NAND_MASK_CLE BIT(22) |
| 30 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 31 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 32 | |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 33 | /* SPL */ |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 34 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 35 | #define CFG_SYS_MASTER_CLOCK 132096000 |
| 36 | #define CFG_SYS_AT91_PLLA 0x20c73f03 |
| 37 | #define CFG_SYS_MCKR 0x1301 |
| 38 | #define CFG_SYS_MCKR_CSS 0x1302 |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 39 | |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 40 | #define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 |
| 41 | #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE |
| 42 | #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 43 | |
| Stefan Roese | dadede5 | 2019-04-02 10:57:27 +0200 | [diff] [blame] | 44 | #endif |