blob: 12e2087c90a313d2297b3dc0e4f8de7fac129eef [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Yong Liang <yong.liang@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
8#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
9
10/* TOPRGU resets */
11#define MT8192_TOPRGU_MM_SW_RST 1
12#define MT8192_TOPRGU_MFG_SW_RST 2
13#define MT8192_TOPRGU_VENC_SW_RST 3
14#define MT8192_TOPRGU_VDEC_SW_RST 4
15#define MT8192_TOPRGU_IMG_SW_RST 5
16#define MT8192_TOPRGU_MD_SW_RST 7
17#define MT8192_TOPRGU_CONN_SW_RST 9
18#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
19#define MT8192_TOPRGU_IPU0_SW_RST 14
20#define MT8192_TOPRGU_IPU1_SW_RST 15
21#define MT8192_TOPRGU_AUDIO_SW_RST 17
22#define MT8192_TOPRGU_CAMSYS_SW_RST 18
23#define MT8192_TOPRGU_MJC_SW_RST 19
24#define MT8192_TOPRGU_C2K_S2_SW_RST 20
25#define MT8192_TOPRGU_C2K_SW_RST 21
26#define MT8192_TOPRGU_PERI_SW_RST 22
27#define MT8192_TOPRGU_PERI_AO_SW_RST 23
28
29#define MT8192_TOPRGU_SW_RST_NUM 23
30
31/* MMSYS resets */
32#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
33
34/* INFRA resets */
35#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
36#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
37#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
38#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
39#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
40
41#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */