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git01.mediatek.com / filogic / uboot / 61412720327b9c2a97e779392616958be72f35f2 / . / arch / arm / include / asm / arch-socfpga / clock_manager.h
blob: babac0e87823799d8db49622f9c3306a1fed69d2 [file] [log] [blame]
Chin Liang Seecb350602014-03-04 22:13:53 -0600[diff] [blame]1/*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CLOCK_MANAGER_H_
8#define _CLOCK_MANAGER_H_
9
10typedef struct {
11 /* main group */
12 uint32_t main_vco_base;
13 uint32_t mpuclk;
14 uint32_t mainclk;
15 uint32_t dbgatclk;
16 uint32_t mainqspiclk;
17 uint32_t mainnandsdmmcclk;
18 uint32_t cfg2fuser0clk;
19 uint32_t maindiv;
20 uint32_t dbgdiv;
21 uint32_t tracediv;
22 uint32_t l4src;
23
24 /* peripheral group */
25 uint32_t peri_vco_base;
26 uint32_t emac0clk;
27 uint32_t emac1clk;
28 uint32_t perqspiclk;
29 uint32_t pernandsdmmcclk;
30 uint32_t perbaseclk;
31 uint32_t s2fuser1clk;
32 uint32_t perdiv;
33 uint32_t gpiodiv;
34 uint32_t persrc;
35
36 /* sdram pll group */
37 uint32_t sdram_vco_base;
38 uint32_t ddrdqsclk;
39 uint32_t ddr2xdqsclk;
40 uint32_t ddrdqclk;
41 uint32_t s2fuser2clk;
42} cm_config_t;
43
44extern void cm_basic_init(const cm_config_t *cfg);
45
Pavel Machek91c2f8f2014-07-19 23:57:59 +0200[diff] [blame]46struct socfpga_clock_manager_main_pll {
47 u32 vco;
48 u32 misc;
49 u32 mpuclk;
50 u32 mainclk;
51 u32 dbgatclk;
52 u32 mainqspiclk;
53 u32 mainnandsdmmcclk;
54 u32 cfgs2fuser0clk;
55 u32 en;
56 u32 maindiv;
57 u32 dbgdiv;
58 u32 tracediv;
59 u32 l4src;
60 u32 stat;
61 u32 _pad_0x38_0x40[2];
62};
63
64struct socfpga_clock_manager_per_pll {
65 u32 vco;
66 u32 misc;
67 u32 emac0clk;
68 u32 emac1clk;
69 u32 perqspiclk;
70 u32 pernandsdmmcclk;
71 u32 perbaseclk;
72 u32 s2fuser1clk;
73 u32 en;
74 u32 div;
75 u32 gpiodiv;
76 u32 src;
77 u32 stat;
78 u32 _pad_0x34_0x40[3];
79};
80
81struct socfpga_clock_manager_sdr_pll {
82 u32 vco;
83 u32 ctrl;
84 u32 ddrdqsclk;
85 u32 ddr2xdqsclk;
86 u32 ddrdqclk;
87 u32 s2fuser2clk;
88 u32 en;
89 u32 stat;
90};
91
Chin Liang Seecb350602014-03-04 22:13:53 -0600[diff] [blame]92struct socfpga_clock_manager {
93 u32 ctrl;
94 u32 bypass;
95 u32 inter;
96 u32 intren;
97 u32 dbctrl;
98 u32 stat;
99 u32 _pad_0x18_0x3f[10];
Pavel Machek91c2f8f2014-07-19 23:57:59 +0200[diff] [blame]100 struct socfpga_clock_manager_main_pll main_pll;
101 struct socfpga_clock_manager_per_pll per_pll;
102 struct socfpga_clock_manager_sdr_pll sdr_pll;
Chin Liang Seecb350602014-03-04 22:13:53 -0600[diff] [blame]103 u32 _pad_0xe0_0x200[72];
Chin Liang Seecb350602014-03-04 22:13:53 -0600[diff] [blame]104};
105
106#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
107#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
108#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
109#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
110#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
111#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
112#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
113#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
114#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
115#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
116#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
117#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
118#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
119#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
120#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
121#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
122#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
123#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
124#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
125#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
126#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
127#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
128#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
129#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
130#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
131#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
132#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
133#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
134#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
135#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
136#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
137#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
138#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
139 (((x) << 0) & 0x000001ff)
140#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
141#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
142#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
143#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
144 (((x) << 0) & 0x000001ff)
145#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
146#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
147#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
148#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
149#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
150#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
151#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
152#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
153#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
154#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
155#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
156#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
157#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
158#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
159#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
160#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
161#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
162#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
163#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
164#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
165#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
166#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
167#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
168#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
169#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
170#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
171#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
172#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
173#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
174#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
175#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
176#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
177#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
178#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
179#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
180#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
181#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
182#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
183#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
184#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
185#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
186#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
187#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
188#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
189#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
190#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
191#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
192#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
193#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
194#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
195#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
196
197#define MAIN_VCO_BASE \
198 (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
199 CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
200
201#define PERI_VCO_BASE \
202 (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
203 CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
204 CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
205
206#define SDR_VCO_BASE \
207 (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
208 CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
209 CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
210
211#endif /* _CLOCK_MANAGER_H_ */