Rajeshwari Shinde | e9e8be8 | 2012-08-24 00:39:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __MAX77686_H_ |
| 25 | #define __MAX77686_H_ |
| 26 | |
| 27 | enum { |
| 28 | MAX77686_REG_PMIC_ID = 0x0, |
| 29 | MAX77686_REG_PMIC_INTSRC, |
| 30 | MAX77686_REG_PMIC_INT1, |
| 31 | MAX77686_REG_PMIC_INT2, |
| 32 | MAX77686_REG_PMIC_INT1MSK, |
| 33 | MAX77686_REG_PMIC_INT2MSK, |
| 34 | |
| 35 | MAX77686_REG_PMIC_STATUS1, |
| 36 | MAX77686_REG_PMIC_STATUS2, |
| 37 | |
| 38 | MAX77686_REG_PMIC_PWRON, |
| 39 | MAX77686_REG_PMIC_ONOFFDELAY, |
| 40 | MAX77686_REG_PMIC_MRSTB, |
| 41 | |
| 42 | MAX77686_REG_PMIC_BUCK1CRTL = 0x10, |
| 43 | MAX77686_REG_PMIC_BUCK1OUT, |
| 44 | MAX77686_REG_PMIC_BUCK2CTRL1, |
| 45 | MAX77686_REG_PMIC_BUCK234FREQ, |
| 46 | MAX77686_REG_PMIC_BUCK2DVS1, |
| 47 | MAX77686_REG_PMIC_BUCK2DVS2, |
| 48 | MAX77686_REG_PMIC_BUCK2DVS3, |
| 49 | MAX77686_REG_PMIC_BUCK2DVS4, |
| 50 | MAX77686_REG_PMIC_BUCK2DVS5, |
| 51 | MAX77686_REG_PMIC_BUCK2DVS6, |
| 52 | MAX77686_REG_PMIC_BUCK2DVS7, |
| 53 | MAX77686_REG_PMIC_BUCK2DVS8, |
| 54 | MAX77686_REG_PMIC_BUCK3CTRL, |
| 55 | MAX77686_REG_PMIC_BUCK3DVS1, |
| 56 | MAX77686_REG_PMIC_BUCK3DVS2, |
| 57 | MAX77686_REG_PMIC_BUCK3DVS3, |
| 58 | MAX77686_REG_PMIC_BUCK3DVS4, |
| 59 | MAX77686_REG_PMIC_BUCK3DVS5, |
| 60 | MAX77686_REG_PMIC_BUCK3DVS6, |
| 61 | MAX77686_REG_PMIC_BUCK3DVS7, |
| 62 | MAX77686_REG_PMIC_BUCK3DVS8, |
| 63 | MAX77686_REG_PMIC_BUCK4CTRL1, |
| 64 | MAX77686_REG_PMIC_BUCK4DVS1 = 0x28, |
| 65 | MAX77686_REG_PMIC_BUCK4DVS2, |
| 66 | MAX77686_REG_PMIC_BUCK4DVS3, |
| 67 | MAX77686_REG_PMIC_BUCK4DVS4, |
| 68 | MAX77686_REG_PMIC_BUCK4DVS5, |
| 69 | MAX77686_REG_PMIC_BUCK4DVS6, |
| 70 | MAX77686_REG_PMIC_BUCK4DVS7, |
| 71 | MAX77686_REG_PMIC_BUCK4DVS8, |
| 72 | MAX77686_REG_PMIC_BUCK5CTRL, |
| 73 | MAX77686_REG_PMIC_BUCK5OUT, |
| 74 | MAX77686_REG_PMIC_BUCK6CRTL, |
| 75 | MAX77686_REG_PMIC_BUCK6OUT, |
| 76 | MAX77686_REG_PMIC_BUCK7CRTL, |
| 77 | MAX77686_REG_PMIC_BUCK7OUT, |
| 78 | MAX77686_REG_PMIC_BUCK8CRTL, |
| 79 | MAX77686_REG_PMIC_BUCK8OUT, |
| 80 | MAX77686_REG_PMIC_BUCK9CRTL, |
| 81 | MAX77686_REG_PMIC_BUCK9OUT, |
| 82 | |
| 83 | MAX77686_REG_PMIC_LDO1CTRL1 = 0x40, |
| 84 | MAX77686_REG_PMIC_LDO2CTRL1, |
| 85 | MAX77686_REG_PMIC_LDO3CTRL1, |
| 86 | MAX77686_REG_PMIC_LDO4CTRL1, |
| 87 | MAX77686_REG_PMIC_LDO5CTRL1, |
| 88 | MAX77686_REG_PMIC_LDO6CTRL1, |
| 89 | MAX77686_REG_PMIC_LDO7CTRL1, |
| 90 | MAX77686_REG_PMIC_LDO8CTRL1, |
| 91 | MAX77686_REG_PMIC_LDO9CTRL1, |
| 92 | MAX77686_REG_PMIC_LDO10CTRL1, |
| 93 | MAX77686_REG_PMIC_LDO11CTRL1, |
| 94 | MAX77686_REG_PMIC_LDO12CTRL1, |
| 95 | MAX77686_REG_PMIC_LDO13CTRL1, |
| 96 | MAX77686_REG_PMIC_LDO14CTRL1, |
| 97 | MAX77686_REG_PMIC_LDO15CTRL1, |
| 98 | MAX77686_REG_PMIC_LDO16CTRL1, |
| 99 | MAX77686_REG_PMIC_LDO17CTRL1, |
| 100 | MAX77686_REG_PMIC_LDO18CTRL1, |
| 101 | MAX77686_REG_PMIC_LDO19CTRL1, |
| 102 | MAX77686_REG_PMIC_LDO20CTRL1, |
| 103 | MAX77686_REG_PMIC_LDO21CTRL1, |
| 104 | MAX77686_REG_PMIC_LDO22CTRL1, |
| 105 | MAX77686_REG_PMIC_LDO23CTRL1, |
| 106 | MAX77686_REG_PMIC_LDO24CTRL1, |
| 107 | MAX77686_REG_PMIC_LDO25CTRL1, |
| 108 | MAX77686_REG_PMIC_LDO26CTRL1, |
| 109 | MAX77686_REG_PMIC_LDO1CTRL2, |
| 110 | MAX77686_REG_PMIC_LDO2CTRL2, |
| 111 | MAX77686_REG_PMIC_LDO3CTRL2, |
| 112 | MAX77686_REG_PMIC_LDO4CTRL2, |
| 113 | MAX77686_REG_PMIC_LDO5CTRL2, |
| 114 | MAX77686_REG_PMIC_LDO6CTRL2, |
| 115 | MAX77686_REG_PMIC_LDO7CTRL2, |
| 116 | MAX77686_REG_PMIC_LDO8CTRL2, |
| 117 | MAX77686_REG_PMIC_LDO9CTRL2, |
| 118 | MAX77686_REG_PMIC_LDO10CTRL2, |
| 119 | MAX77686_REG_PMIC_LDO11CTRL2, |
| 120 | MAX77686_REG_PMIC_LDO12CTRL2, |
| 121 | MAX77686_REG_PMIC_LDO13CTRL2, |
| 122 | MAX77686_REG_PMIC_LDO14CTRL2, |
| 123 | MAX77686_REG_PMIC_LDO15CTRL2, |
| 124 | MAX77686_REG_PMIC_LDO16CTRL2, |
| 125 | MAX77686_REG_PMIC_LDO17CTRL2, |
| 126 | MAX77686_REG_PMIC_LDO18CTRL2, |
| 127 | MAX77686_REG_PMIC_LDO19CTRL2, |
| 128 | MAX77686_REG_PMIC_LDO20CTRL2, |
| 129 | MAX77686_REG_PMIC_LDO21CTRL2, |
| 130 | MAX77686_REG_PMIC_LDO22CTRL2, |
| 131 | MAX77686_REG_PMIC_LDO23CTRL2, |
| 132 | MAX77686_REG_PMIC_LDO24CTRL2, |
| 133 | MAX77686_REG_PMIC_LDO25CTRL2, |
| 134 | MAX77686_REG_PMIC_LDO26CTRL2, |
| 135 | |
| 136 | MAX77686_REG_PMIC_BBAT = 0x7e, |
| 137 | MAX77686_REG_PMIC_32KHZ, |
| 138 | |
| 139 | PMIC_NUM_OF_REGS, |
| 140 | }; |
| 141 | |
| 142 | /* I2C device address for pmic max77686 */ |
| 143 | #define MAX77686_I2C_ADDR (0x12 >> 1) |
| 144 | |
| 145 | enum { |
| 146 | REG_DISABLE = 0, |
| 147 | REG_ENABLE |
| 148 | }; |
| 149 | |
| 150 | enum { |
| 151 | LDO_OFF = 0, |
| 152 | LDO_ON, |
| 153 | |
| 154 | DIS_LDO = (0x00 << 6), |
| 155 | EN_LDO = (0x3 << 6), |
| 156 | }; |
| 157 | |
Rajeshwari Shinde | 0bdb3fb | 2013-02-12 20:40:02 +0000 | [diff] [blame] | 158 | /* Buck1 1 volt value */ |
| 159 | #define MAX77686_BUCK1OUT_1V 0x5 |
| 160 | #define MAX77686_BUCK1CTRL_EN (3 << 0) |
| 161 | /* Buck2 1.3 volt value */ |
| 162 | #define MAX77686_BUCK2DVS1_1_3V 0x38 |
| 163 | #define MAX77686_BUCK2CTRL_ON (1 << 4) |
| 164 | /* Buck3 1.0125 volt value */ |
| 165 | #define MAX77686_BUCK3DVS1_1_0125V 0x21 |
| 166 | #define MAX77686_BUCK3CTRL_ON (1 << 4) |
| 167 | /* Buck4 1.2 volt value */ |
| 168 | #define MAX77686_BUCK4DVS1_1_2V 0x30 |
| 169 | #define MAX77686_BUCK4CTRL_ON (1 << 4) |
| 170 | /* LDO2 1.5 volt value */ |
| 171 | #define MAX77686_LD02CTRL1_1_5V 0x1c |
| 172 | /* LDO3 1.8 volt value */ |
| 173 | #define MAX77686_LD03CTRL1_1_8V 0x14 |
| 174 | /* LDO5 1.8 volt value */ |
| 175 | #define MAX77686_LD05CTRL1_1_8V 0x14 |
| 176 | /* LDO10 1.8 volt value */ |
| 177 | #define MAX77686_LD10CTRL1_1_8V 0x14 |
| 178 | /* |
| 179 | * MAX77686_REG_PMIC_32KHZ set to 32KH CP |
| 180 | * output is activated |
| 181 | */ |
| 182 | #define MAX77686_32KHCP_EN (1 << 1) |
| 183 | /* |
| 184 | * MAX77686_REG_PMIC_BBAT set to |
| 185 | * Back up batery charger on and |
| 186 | * limit voltage setting to 3.5v |
| 187 | */ |
| 188 | #define MAX77686_BBCHOSTEN (1 << 0) |
| 189 | #define MAX77686_BBCVS_3_5V (3 << 3) |
Rajeshwari Shinde | e9e8be8 | 2012-08-24 00:39:23 +0000 | [diff] [blame] | 190 | #endif /* __MAX77686_PMIC_H_ */ |