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wdenk7a428cc2003-06-15 22:40:42 +00001/*
Jerry Huang0caea1a2010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Flemingad347bb2008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk7a428cc2003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Thomas Chou225d4c02011-04-19 03:48:31 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk7a428cc2003-06-15 22:40:42 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk7a428cc2003-06-15 22:40:42 +000028
Andy Flemingad347bb2008-10-30 16:41:01 -050029#include <linux/list.h>
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +000030#include <linux/compiler.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050031
32#define SD_VERSION_SD 0x20000
Jaehoon Chung6108ef62013-01-29 19:31:16 +000033#define SD_VERSION_2 (SD_VERSION_SD | 0x200)
34#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100)
35#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
Andy Flemingad347bb2008-10-30 16:41:01 -050036#define MMC_VERSION_MMC 0x10000
37#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
Jaehoon Chung6108ef62013-01-29 19:31:16 +000038#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102)
39#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104)
40#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202)
41#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300)
42#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400)
43#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401)
44#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402)
45#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
46#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
47#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
Andy Flemingad347bb2008-10-30 16:41:01 -050048
49#define MMC_MODE_HS 0x001
50#define MMC_MODE_HS_52MHz 0x010
51#define MMC_MODE_4BIT 0x100
52#define MMC_MODE_8BIT 0x200
Thomas Chou1254c3d2010-12-24 13:12:21 +000053#define MMC_MODE_SPI 0x400
Łukasz Majewski237823e2011-07-05 02:19:44 +000054#define MMC_MODE_HC 0x800
Andy Flemingad347bb2008-10-30 16:41:01 -050055
Łukasz Majewskib6fe0dc2012-03-12 22:07:18 +000056#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
57#define MMC_MODE_WIDTH_BITS_SHIFT 8
58
Andy Flemingad347bb2008-10-30 16:41:01 -050059#define SD_DATA_4BIT 0x00040000
60
Albin Tonnerre06f9db12009-08-22 14:21:53 +020061#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Flemingad347bb2008-10-30 16:41:01 -050062
63#define MMC_DATA_READ 1
64#define MMC_DATA_WRITE 2
65
66#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
67#define UNUSABLE_ERR -17 /* Unusable Card */
68#define COMM_ERR -18 /* Communications Error */
69#define TIMEOUT -19
70
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020071#define MMC_CMD_GO_IDLE_STATE 0
72#define MMC_CMD_SEND_OP_COND 1
73#define MMC_CMD_ALL_SEND_CID 2
74#define MMC_CMD_SET_RELATIVE_ADDR 3
75#define MMC_CMD_SET_DSR 4
Andy Flemingad347bb2008-10-30 16:41:01 -050076#define MMC_CMD_SWITCH 6
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020077#define MMC_CMD_SELECT_CARD 7
Andy Flemingad347bb2008-10-30 16:41:01 -050078#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020079#define MMC_CMD_SEND_CSD 9
80#define MMC_CMD_SEND_CID 10
Andy Flemingad347bb2008-10-30 16:41:01 -050081#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020082#define MMC_CMD_SEND_STATUS 13
83#define MMC_CMD_SET_BLOCKLEN 16
84#define MMC_CMD_READ_SINGLE_BLOCK 17
85#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Flemingad347bb2008-10-30 16:41:01 -050086#define MMC_CMD_WRITE_SINGLE_BLOCK 24
87#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wenea526762011-06-22 17:03:31 +000088#define MMC_CMD_ERASE_GROUP_START 35
89#define MMC_CMD_ERASE_GROUP_END 36
90#define MMC_CMD_ERASE 38
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020091#define MMC_CMD_APP_CMD 55
Thomas Chou1254c3d2010-12-24 13:12:21 +000092#define MMC_CMD_SPI_READ_OCR 58
93#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020094
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020095#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Flemingad347bb2008-10-30 16:41:01 -050096#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020097#define SD_CMD_SEND_IF_COND 8
98
99#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wenea526762011-06-22 17:03:31 +0000100#define SD_CMD_ERASE_WR_BLK_START 32
101#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200102#define SD_CMD_APP_SEND_OP_COND 41
Andy Flemingad347bb2008-10-30 16:41:01 -0500103#define SD_CMD_APP_SEND_SCR 51
104
105/* SCR definitions in different words */
106#define SD_HIGHSPEED_BUSY 0x00020000
107#define SD_HIGHSPEED_SUPPORTED 0x00020000
108
109#define MMC_HS_TIMING 0x00000100
110#define MMC_HS_52MHZ 0x2
111
Thomas Chou225d4c02011-04-19 03:48:31 +0000112#define OCR_BUSY 0x80000000
113#define OCR_HCS 0x40000000
Raffaele Recalcati1df837e2011-03-11 02:01:13 +0000114#define OCR_VOLTAGE_MASK 0x007FFF80
115#define OCR_ACCESS_MODE 0x60000000
Andy Flemingad347bb2008-10-30 16:41:01 -0500116
Lei Wenea526762011-06-22 17:03:31 +0000117#define SECURE_ERASE 0x80000000
118
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000119#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chou225d4c02011-04-19 03:48:31 +0000120#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
121#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Chou45385002011-04-19 03:48:32 +0000122#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000123
Jan Kloetzke31789322012-02-05 22:29:12 +0000124#define MMC_STATE_PRG (7 << 9)
125
Andy Flemingad347bb2008-10-30 16:41:01 -0500126#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
127#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
128#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
129#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
130#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
131#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
132#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
133#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
134#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
135#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
136#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
137#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
138#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
139#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
140#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
141#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
142#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
143
144#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
145#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
146 addressed by index which are
147 1 in value field */
148#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
149 addressed by index, which are
150 1 in value field */
151#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
152
153#define SD_SWITCH_CHECK 0
154#define SD_SWITCH_SWITCH 1
155
156/*
157 * EXT_CSD fields
158 */
Lei Wen217467f2011-10-03 20:35:10 +0000159#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
160#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
161#define EXT_CSD_PART_CONF 179 /* R/W */
162#define EXT_CSD_BUS_WIDTH 183 /* R/W */
163#define EXT_CSD_HS_TIMING 185 /* R/W */
164#define EXT_CSD_REV 192 /* RO */
165#define EXT_CSD_CARD_TYPE 196 /* RO */
166#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
167#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren009784c2012-07-30 10:55:43 +0000168#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Flemingad347bb2008-10-30 16:41:01 -0500169
170/*
171 * EXT_CSD field definitions
172 */
173
Thomas Chou225d4c02011-04-19 03:48:31 +0000174#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
175#define EXT_CSD_CMD_SET_SECURE (1 << 1)
176#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Flemingad347bb2008-10-30 16:41:01 -0500177
Thomas Chou225d4c02011-04-19 03:48:31 +0000178#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
179#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Flemingad347bb2008-10-30 16:41:01 -0500180
181#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
182#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
183#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200184
Andy Fleming724ecf02008-10-30 16:31:39 -0500185#define R1_ILLEGAL_COMMAND (1 << 22)
186#define R1_APP_CMD (1 << 5)
187
Andy Flemingad347bb2008-10-30 16:41:01 -0500188#define MMC_RSP_PRESENT (1 << 0)
Thomas Chou225d4c02011-04-19 03:48:31 +0000189#define MMC_RSP_136 (1 << 1) /* 136 bit response */
190#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
191#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
192#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Flemingad347bb2008-10-30 16:41:01 -0500193
Thomas Chou225d4c02011-04-19 03:48:31 +0000194#define MMC_RSP_NONE (0)
195#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Flemingad347bb2008-10-30 16:41:01 -0500196#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
197 MMC_RSP_BUSY)
Thomas Chou225d4c02011-04-19 03:48:31 +0000198#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
199#define MMC_RSP_R3 (MMC_RSP_PRESENT)
200#define MMC_RSP_R4 (MMC_RSP_PRESENT)
201#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
202#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
203#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Flemingad347bb2008-10-30 16:41:01 -0500204
Lei Wen31b99802011-05-02 16:26:26 +0000205#define MMCPART_NOAVAILABLE (0xff)
206#define PART_ACCESS_MASK (0x7)
207#define PART_SUPPORT (0x1)
wdenk7a428cc2003-06-15 22:40:42 +0000208
Andy Fleming724ecf02008-10-30 16:31:39 -0500209struct mmc_cid {
210 unsigned long psn;
211 unsigned short oid;
212 unsigned char mid;
213 unsigned char prv;
214 unsigned char mdt;
215 char pnm[7];
216};
217
Andy Flemingad347bb2008-10-30 16:41:01 -0500218struct mmc_cmd {
219 ushort cmdidx;
220 uint resp_type;
221 uint cmdarg;
Rabin Vincentbdf7a682009-04-05 13:30:55 +0530222 uint response[4];
Andy Flemingad347bb2008-10-30 16:41:01 -0500223};
224
225struct mmc_data {
226 union {
227 char *dest;
228 const char *src; /* src buffers don't get written to */
229 };
230 uint flags;
231 uint blocks;
232 uint blocksize;
233};
234
235struct mmc {
236 struct list_head link;
237 char name[32];
238 void *priv;
239 uint voltages;
240 uint version;
Lei Wen31b99802011-05-02 16:26:26 +0000241 uint has_init;
Andy Flemingad347bb2008-10-30 16:41:01 -0500242 uint f_min;
243 uint f_max;
244 int high_capacity;
245 uint bus_width;
246 uint clock;
247 uint card_caps;
248 uint host_caps;
249 uint ocr;
250 uint scr[2];
251 uint csd[4];
Rabin Vincentbdf7a682009-04-05 13:30:55 +0530252 uint cid[4];
Andy Flemingad347bb2008-10-30 16:41:01 -0500253 ushort rca;
Lei Wen31b99802011-05-02 16:26:26 +0000254 char part_config;
255 char part_num;
Andy Flemingad347bb2008-10-30 16:41:01 -0500256 uint tran_speed;
257 uint read_bl_len;
258 uint write_bl_len;
Lei Wenea526762011-06-22 17:03:31 +0000259 uint erase_grp_size;
Andy Flemingad347bb2008-10-30 16:41:01 -0500260 u64 capacity;
261 block_dev_desc_t block_dev;
262 int (*send_cmd)(struct mmc *mmc,
263 struct mmc_cmd *cmd, struct mmc_data *data);
264 void (*set_ios)(struct mmc *mmc);
265 int (*init)(struct mmc *mmc);
Thierry Redingb9c8b772012-01-02 01:15:37 +0000266 int (*getcd)(struct mmc *mmc);
Nikita Kiryanov020f2612012-12-03 02:19:46 +0000267 int (*getwp)(struct mmc *mmc);
Sandeep Paulraj50347172010-12-20 20:01:21 -0500268 uint b_max;
Andy Flemingad347bb2008-10-30 16:41:01 -0500269};
270
271int mmc_register(struct mmc *mmc);
272int mmc_initialize(bd_t *bis);
273int mmc_init(struct mmc *mmc);
274int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang0caea1a2010-11-25 17:06:07 +0000275void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Flemingad347bb2008-10-30 16:41:01 -0500276struct mmc *find_mmc_device(int dev_num);
Steve Sakomane4548302010-07-01 12:12:42 -0700277int mmc_set_dev(int dev_num);
Andy Flemingad347bb2008-10-30 16:41:01 -0500278void print_mmc_devices(char separator);
Lei Wend430d7c2011-05-02 16:26:25 +0000279int get_mmc_num(void);
Thierry Redingd7aebf42012-01-02 01:15:36 +0000280int board_mmc_getcd(struct mmc *mmc);
Lei Wen31b99802011-05-02 16:26:26 +0000281int mmc_switch_part(int dev_num, unsigned int part_num);
Thierry Redingb9c8b772012-01-02 01:15:37 +0000282int mmc_getcd(struct mmc *mmc);
Nikita Kiryanov020f2612012-12-03 02:19:46 +0000283int mmc_getwp(struct mmc *mmc);
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +0000284void spl_mmc_load(void) __noreturn;
Andy Flemingad347bb2008-10-30 16:41:01 -0500285
Reinhard Meyerc718a562010-08-13 10:31:06 +0200286#ifdef CONFIG_GENERIC_MMC
Thomas Chou1254c3d2010-12-24 13:12:21 +0000287#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
288struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyerc718a562010-08-13 10:31:06 +0200289#else
Andy Flemingad347bb2008-10-30 16:41:01 -0500290int mmc_legacy_init(int verbose);
291#endif
Reinhard Meyerc718a562010-08-13 10:31:06 +0200292
wdenk7a428cc2003-06-15 22:40:42 +0000293#endif /* _MMC_H_ */