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wdenk591dda52002-11-18 00:14:45 +00001/*
Graeme Russ45fc1d82011-04-13 19:43:26 +10002 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
wdenk591dda52002-11-18 00:14:45 +00005 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +00007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
wdenk591dda52002-11-18 00:14:45 +000027#include <common.h>
wdenk591dda52002-11-18 00:14:45 +000028#include <asm/io.h>
Graeme Russ93efcb22011-02-12 15:11:32 +110029#include <asm/processor-flags.h>
wdenk591dda52002-11-18 00:14:45 +000030#include <asm/ic/sc520.h>
31
Wolfgang Denk6405a152006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
Graeme Russb112bca2011-02-12 15:11:36 +110034sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
wdenk591dda52002-11-18 00:14:45 +000035
Graeme Russ121931c2011-02-12 15:11:35 +110036int cpu_init_f(void)
wdenk591dda52002-11-18 00:14:45 +000037{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038 if (CONFIG_SYS_SC520_HIGH_SPEED) {
Graeme Russ3e6ec382010-10-07 20:03:21 +110039 /* set it to 133 MHz and write back */
40 writeb(0x02, &sc520_mmcr->cpuctl);
wdenk591dda52002-11-18 00:14:45 +000041 gd->cpu_clk = 133000000;
wdenk591dda52002-11-18 00:14:45 +000042 } else {
Graeme Russ3e6ec382010-10-07 20:03:21 +110043 /* set it to 100 MHz and write back */
44 writeb(0x01, &sc520_mmcr->cpuctl);
wdenk591dda52002-11-18 00:14:45 +000045 gd->cpu_clk = 100000000;
46 }
wdenk57b2d802003-06-27 21:31:46 +000047
wdenk591dda52002-11-18 00:14:45 +000048 /* wait at least one millisecond */
Graeme Russ3e6ec382010-10-07 20:03:21 +110049 asm("movl $0x2000, %%ecx\n"
Graeme Russde7f9382009-08-23 12:59:46 +100050 "0: pushl %%ecx\n"
wdenk591dda52002-11-18 00:14:45 +000051 "popl %%ecx\n"
Graeme Russde7f9382009-08-23 12:59:46 +100052 "loop 0b\n": : : "ecx");
wdenk591dda52002-11-18 00:14:45 +000053
Graeme Russ121931c2011-02-12 15:11:35 +110054 return x86_cpu_init_f();
wdenk591dda52002-11-18 00:14:45 +000055}
56
Graeme Russ151713d2011-02-12 15:12:12 +110057int cpu_init_r(void)
58{
59 /* Disable the PAR used for CAR */
60 writel(0x0000000, &sc520_mmcr->par[2]);
61
62 /* turn on the SDRAM write buffer */
63 writeb(0x11, &sc520_mmcr->dbctl);
64
65 return x86_cpu_init_r();
66}