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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roesee373c5f2009-01-21 17:24:49 +01002/*
3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 *
5 * Copyright (C) 2006 Micronas GmbH
Stefan Roesee373c5f2009-01-21 17:24:49 +01006 */
7
8#include <common.h>
9#include <command.h>
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070010#include <netdev.h>
Stefan Roesee373c5f2009-01-21 17:24:49 +010011#include <asm/mipsregs.h>
12#include "vct.h"
13
14#if defined(CONFIG_VCT_PREMIUM)
15#define BOARD_NAME "PremiumD"
16#elif defined(CONFIG_VCT_PLATINUM)
17#define BOARD_NAME "PlatinumD"
18#elif defined(CONFIG_VCT_PLATINUMAVC)
19#define BOARD_NAME "PlatinumAVC"
20#else
21#error "vct: No board variant defined!"
22#endif
23
24#if defined(CONFIG_VCT_ONENAND)
25#define BOARD_NAME_ADD " OneNAND"
26#else
27#define BOARD_NAME_ADD " NOR"
28#endif
29
Simon Glass39f90ba2017-03-31 08:40:25 -060030DECLARE_GLOBAL_DATA_PTR;
31
Stefan Roesee373c5f2009-01-21 17:24:49 +010032int board_early_init_f(void)
33{
34 /*
35 * First initialize the PIN mulitplexing
36 */
37 vct_pin_mux_initialize();
38
39 /*
40 * Init the EBI very early so that FLASH can be accessed
41 */
42 ebi_initialize();
43
44 return 0;
45}
46
47void _machine_restart(void)
48{
49 reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
50 reg_write(WDT_TORR(WDT_BASE), 0x00);
51 reg_write(WDT_CR(WDT_BASE), 0x1D);
52
53 /*
54 * Now wait for the watchdog to trigger the reset
55 */
56 udelay(1000000);
57}
58
59/*
60 * SDRAM is already configured by the bootstrap code, only return the
61 * auto-detected size here
62 */
Simon Glassd35f3382017-04-06 12:47:05 -060063int dram_init(void)
Stefan Roesee373c5f2009-01-21 17:24:49 +010064{
Simon Glass39f90ba2017-03-31 08:40:25 -060065 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
Stefan Roesee373c5f2009-01-21 17:24:49 +010066 CONFIG_SYS_MBYTES_SDRAM << 20);
Simon Glass39f90ba2017-03-31 08:40:25 -060067
68 return 0;
Stefan Roesee373c5f2009-01-21 17:24:49 +010069}
70
71int checkboard(void)
72{
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000073 char buf[64];
Simon Glass64b723f2017-08-03 12:22:12 -060074 int i = env_get_f("serial#", buf, sizeof(buf));
Stefan Roesee373c5f2009-01-21 17:24:49 +010075 u32 config0 = read_c0_prid();
Stefan Roesee373c5f2009-01-21 17:24:49 +010076
77 if ((config0 & 0xff0000) == PRID_COMP_LEGACY
78 && (config0 & 0xff00) == PRID_IMP_LX4280) {
79 puts("Board: MDED \n");
80 printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
81 (config0 >> 8) & 0xFF, config0 & 0xFF);
82 } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
83 && (config0 & 0xff00) == PRID_IMP_VGC) {
84 u32 jedec_id = *((u32 *) 0xBEBC71A0);
85 if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
86 puts("Board: VGCA \n");
87 } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
88 || (((jedec_id) >> 12) & 0xFF) == 0x49) {
89 puts("Board: VGCB \n");
90 }
91 printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
92 (config0 >> 8) & 0xFF, config0 & 0xFF);
93 } else if (config0 == 0x19378) {
94 printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
95 (config0 >> 8) & 0xFF, config0 & 0xFF);
96 } else {
97 printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
98 config0);
99 }
100
101 printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000102 if (i > 0) {
Stefan Roesee373c5f2009-01-21 17:24:49 +0100103 puts(", serial# ");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000104 puts(buf);
Stefan Roesee373c5f2009-01-21 17:24:49 +0100105 }
106 putc('\n');
107
108 return 0;
109}
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700110
111int board_eth_init(bd_t *bis)
112{
113 int rc = 0;
114#ifdef CONFIG_SMC911X
115 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
116#endif
117 return rc;
118}