Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Board functions for Gumstix Pepper and AM335x-based boards |
| 4 | * |
| 5 | * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ |
| 6 | * Based on board/ti/am335x/board.c from Texas Instruments, Inc. |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 10 | #include <env.h> |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 11 | #include <errno.h> |
Simon Glass | 3673618 | 2019-11-14 12:57:24 -0700 | [diff] [blame] | 12 | #include <serial.h> |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 13 | #include <spl.h> |
| 14 | #include <asm/arch/cpu.h> |
| 15 | #include <asm/arch/hardware.h> |
| 16 | #include <asm/arch/omap.h> |
| 17 | #include <asm/arch/ddr_defs.h> |
| 18 | #include <asm/arch/clock.h> |
| 19 | #include <asm/arch/gpio.h> |
| 20 | #include <asm/arch/mmc_host_def.h> |
| 21 | #include <asm/arch/sys_proto.h> |
| 22 | #include <asm/arch/mem.h> |
| 23 | #include <asm/io.h> |
| 24 | #include <asm/emif.h> |
| 25 | #include <asm/gpio.h> |
| 26 | #include <i2c.h> |
| 27 | #include <miiphy.h> |
| 28 | #include <cpsw.h> |
| 29 | #include <power/tps65217.h> |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 30 | #include <watchdog.h> |
| 31 | #include "board.h" |
| 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | #ifdef CONFIG_SPL_BUILD |
Adam YH Lee | 3dc3c98 | 2015-06-01 14:29:09 -0700 | [diff] [blame] | 36 | #define OSC (V_OSCK/1000000) |
| 37 | |
| 38 | static const struct ddr_data ddr3_data = { |
| 39 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, |
| 40 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
| 41 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
| 42 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
| 43 | }; |
| 44 | |
| 45 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
| 46 | .cmd0csratio = MT41K256M16HA125E_RATIO, |
| 47 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 48 | |
| 49 | .cmd1csratio = MT41K256M16HA125E_RATIO, |
| 50 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 51 | |
| 52 | .cmd2csratio = MT41K256M16HA125E_RATIO, |
| 53 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 54 | }; |
| 55 | |
| 56 | static struct emif_regs ddr3_emif_reg_data = { |
| 57 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
| 58 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
| 59 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
| 60 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
| 61 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
| 62 | .zq_config = MT41K256M16HA125E_ZQ_CFG, |
| 63 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
| 64 | }; |
| 65 | |
| 66 | const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1}; |
| 67 | |
| 68 | const struct ctrl_ioregs ioregs_ddr3 = { |
| 69 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 70 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 71 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 72 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 73 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 74 | }; |
| 75 | |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 76 | static const struct ddr_data ddr2_data = { |
Tom Rini | 7f50a57 | 2014-07-07 21:40:16 -0400 | [diff] [blame] | 77 | .datardsratio0 = MT47H128M16RT25E_RD_DQS, |
| 78 | .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, |
| 79 | .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | static const struct cmd_control ddr2_cmd_ctrl_data = { |
| 83 | .cmd0csratio = MT47H128M16RT25E_RATIO, |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 84 | |
| 85 | .cmd1csratio = MT47H128M16RT25E_RATIO, |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 86 | |
| 87 | .cmd2csratio = MT47H128M16RT25E_RATIO, |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | static const struct emif_regs ddr2_emif_reg_data = { |
| 91 | .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
| 92 | .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
| 93 | .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
| 94 | .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
| 95 | .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
| 96 | .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
| 97 | }; |
| 98 | |
Adam YH Lee | 3dc3c98 | 2015-06-01 14:29:09 -0700 | [diff] [blame] | 99 | const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1}; |
| 100 | |
| 101 | const struct ctrl_ioregs ioregs_ddr2 = { |
| 102 | .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 103 | .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 104 | .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 105 | .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 106 | .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 107 | }; |
| 108 | |
| 109 | static int read_eeprom(struct pepper_board_id *header) |
| 110 | { |
| 111 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
| 112 | return -ENODEV; |
| 113 | } |
| 114 | |
| 115 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, |
| 116 | sizeof(struct pepper_board_id))) { |
| 117 | return -EIO; |
| 118 | } |
| 119 | |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | const struct dpll_params *get_dpll_ddr_params(void) |
| 124 | { |
| 125 | struct pepper_board_id header; |
| 126 | |
| 127 | enable_i2c0_pin_mux(); |
| 128 | i2c_set_bus_num(0); |
| 129 | |
| 130 | if (read_eeprom(&header) < 0) |
| 131 | return &dpll_ddr3; |
| 132 | |
| 133 | switch (header.device_vendor) { |
| 134 | case GUMSTIX_PEPPER: |
| 135 | return &dpll_ddr2; |
| 136 | case GUMSTIX_PEPPER_DVI: |
| 137 | return &dpll_ddr3; |
| 138 | default: |
| 139 | return &dpll_ddr3; |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | void sdram_init(void) |
| 144 | { |
| 145 | const struct dpll_params *dpll = get_dpll_ddr_params(); |
| 146 | |
| 147 | /* |
| 148 | * Here we are assuming PLL clock reveals the type of RAM. |
| 149 | * DDR2 = 266 |
| 150 | * DDR3 = 400 |
| 151 | * Note that DDR3 is the default. |
| 152 | */ |
| 153 | if (dpll->m == 266) { |
| 154 | config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data, |
| 155 | &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); |
| 156 | } |
| 157 | else if (dpll->m == 400) { |
| 158 | config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data, |
| 159 | &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); |
| 160 | } |
| 161 | } |
| 162 | |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 163 | #ifdef CONFIG_SPL_OS_BOOT |
| 164 | int spl_start_uboot(void) |
| 165 | { |
| 166 | /* break into full u-boot on 'c' */ |
| 167 | return serial_tstc() && serial_getc() == 'c'; |
| 168 | } |
| 169 | #endif |
| 170 | |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 171 | void set_uart_mux_conf(void) |
| 172 | { |
| 173 | enable_uart0_pin_mux(); |
| 174 | } |
| 175 | |
| 176 | void set_mux_conf_regs(void) |
| 177 | { |
| 178 | enable_board_pin_mux(); |
| 179 | } |
| 180 | |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 181 | |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 182 | #endif |
| 183 | |
| 184 | int board_init(void) |
| 185 | { |
| 186 | #if defined(CONFIG_HW_WATCHDOG) |
| 187 | hw_watchdog_init(); |
| 188 | #endif |
| 189 | |
| 190 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 191 | gpmc_init(); |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 197 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
| 198 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 199 | |
| 200 | static void cpsw_control(int enabled) |
| 201 | { |
| 202 | /* VTP can be added here */ |
| 203 | |
| 204 | return; |
| 205 | } |
| 206 | |
| 207 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 208 | { |
| 209 | .slave_reg_ofs = 0x208, |
| 210 | .sliver_reg_ofs = 0xd80, |
| 211 | .phy_addr = 0, |
| 212 | .phy_if = PHY_INTERFACE_MODE_RGMII, |
| 213 | }, |
| 214 | }; |
| 215 | |
| 216 | static struct cpsw_platform_data cpsw_data = { |
| 217 | .mdio_base = CPSW_MDIO_BASE, |
| 218 | .cpsw_base = CPSW_BASE, |
| 219 | .mdio_div = 0xff, |
| 220 | .channels = 8, |
| 221 | .cpdma_reg_ofs = 0x800, |
| 222 | .slaves = 1, |
| 223 | .slave_data = cpsw_slaves, |
| 224 | .ale_reg_ofs = 0xd00, |
| 225 | .ale_entries = 1024, |
| 226 | .host_port_reg_ofs = 0x108, |
| 227 | .hw_stats_reg_ofs = 0x900, |
| 228 | .bd_ram_ofs = 0x2000, |
| 229 | .mac_control = (1 << 5), |
| 230 | .control = cpsw_control, |
| 231 | .host_port_num = 0, |
| 232 | .version = CPSW_CTRL_VERSION_2, |
| 233 | }; |
| 234 | |
| 235 | int board_eth_init(bd_t *bis) |
| 236 | { |
| 237 | int rv, n = 0; |
| 238 | uint8_t mac_addr[6]; |
| 239 | uint32_t mac_hi, mac_lo; |
| 240 | const char *devname; |
| 241 | |
Simon Glass | 399a9ce | 2017-08-03 12:22:14 -0600 | [diff] [blame] | 242 | if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 243 | /* try reading mac address from efuse */ |
| 244 | mac_lo = readl(&cdev->macid0l); |
| 245 | mac_hi = readl(&cdev->macid0h); |
| 246 | mac_addr[0] = mac_hi & 0xFF; |
| 247 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 248 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 249 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 250 | mac_addr[4] = mac_lo & 0xFF; |
| 251 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 252 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 253 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Ash Charles | 9cb110e | 2014-05-07 08:24:11 -0700 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
| 257 | |
| 258 | rv = cpsw_register(&cpsw_data); |
| 259 | if (rv < 0) |
| 260 | printf("Error %d registering CPSW switch\n", rv); |
| 261 | else |
| 262 | n += rv; |
| 263 | |
| 264 | /* |
| 265 | * |
| 266 | * CPSW RGMII Internal Delay Mode is not supported in all PVT |
| 267 | * operating points. So we must set the TX clock delay feature |
| 268 | * in the KSZ9021 PHY. Since we only support a single ethernet |
| 269 | * device in U-Boot, we only do this for the current instance. |
| 270 | */ |
| 271 | devname = miiphy_get_current_dev(); |
| 272 | /* max rx/tx clock delay, min rx/tx control delay */ |
| 273 | miiphy_write(devname, 0x0, 0x0b, 0x8104); |
| 274 | miiphy_write(devname, 0x0, 0xc, 0xa0a0); |
| 275 | |
| 276 | /* min rx data delay */ |
| 277 | miiphy_write(devname, 0x0, 0x0b, 0x8105); |
| 278 | miiphy_write(devname, 0x0, 0x0c, 0x0000); |
| 279 | |
| 280 | /* min tx data delay */ |
| 281 | miiphy_write(devname, 0x0, 0x0b, 0x8106); |
| 282 | miiphy_write(devname, 0x0, 0x0c, 0x0000); |
| 283 | |
| 284 | return n; |
| 285 | } |
| 286 | #endif |