blob: e1eddbff95340630450a97b10d3ba636e679c89c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fan81590632016-08-11 14:02:57 +08002/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fan81590632016-08-11 14:02:57 +08004 */
5
Simon Glassa7b51302019-11-14 12:57:46 -07006#include <init.h>
Peng Fan81590632016-08-11 14:02:57 +08007#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6-pins.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020014#include <asm/mach-imx/iomux-v3.h>
15#include <asm/mach-imx/boot_mode.h>
Peng Fan81590632016-08-11 14:02:57 +080016#include <asm/io.h>
17#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060018#include <env.h>
Yangbo Lu73340382019-06-21 11:42:28 +080019#include <fsl_esdhc_imx.h>
Peng Fan81590632016-08-11 14:02:57 +080020#include <linux/sizes.h>
21#include <mmc.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28
29int dram_init(void)
30{
31 gd->ram_size = imx_ddr_size();
32
33 return 0;
34}
35
36static iomux_v3_cfg_t const uart1_pads[] = {
37 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
38 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
39};
40
41static void setup_iomux_uart(void)
42{
43 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
44}
45
46int board_mmc_get_env_dev(int devno)
47{
48 return devno;
49}
50
51int mmc_map_to_kernel_blk(int devno)
52{
53 return devno;
54}
55
56int board_early_init_f(void)
57{
58 setup_iomux_uart();
59
60 return 0;
61}
62
63int board_init(void)
64{
65 /* Address of boot parameters */
66 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
67
68 return 0;
69}
70
71#ifdef CONFIG_CMD_BMODE
72static const struct boot_mode board_boot_modes[] = {
73 /* 4 bit bus width */
74 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
75 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
76 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
77 {NULL, 0},
78};
79#endif
80
81int board_late_init(void)
82{
83#ifdef CONFIG_CMD_BMODE
84 add_board_boot_modes(board_boot_modes);
85#endif
86
87#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Peng Fan5098eae2019-08-08 09:55:57 +000088 if (is_cpu_type(MXC_CPU_MX6ULZ))
89 env_set("board_name", "ULZ-EVK");
90 else
91 env_set("board_name", "EVK");
Simon Glass6a38e412017-08-03 12:22:09 -060092 env_set("board_rev", "14X14");
Peng Fan81590632016-08-11 14:02:57 +080093#endif
94
95 return 0;
96}
97
98int checkboard(void)
99{
Peng Fan5098eae2019-08-08 09:55:57 +0000100 if (is_cpu_type(MXC_CPU_MX6ULZ))
101 puts("Board: MX6ULZ 14x14 EVK\n");
102 else
103 puts("Board: MX6ULL 14x14 EVK\n");
Peng Fan81590632016-08-11 14:02:57 +0800104
105 return 0;
106}