blob: 06ea8775044a1128c323c00397b0b7f60e0dc505 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05302/* Copyright 2013 Freescale Semiconductor, Inc.
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05303 */
4
5#include <common.h>
Simon Glassa73bda42015-11-08 23:47:45 -07006#include <console.h>
Simon Glass79fd2142019-08-01 09:46:43 -06007#include <env.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05309#include <asm/spl.h>
10#include <malloc.h>
11#include <ns16550.h>
12#include <nand.h>
13#include <i2c.h>
14#include "../common/qixis.h"
15#include "b4860qds_qixis.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19phys_size_t get_effective_memsize(void)
20{
21 return CONFIG_SYS_L3_SIZE;
22}
23
24unsigned long get_board_sys_clk(void)
25{
26 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
27
28 switch ((sysclk_conf & 0x0C) >> 2) {
29 case QIXIS_CLK_100:
30 return 100000000;
31 case QIXIS_CLK_125:
32 return 125000000;
33 case QIXIS_CLK_133:
34 return 133333333;
35 }
36 return 66666666;
37}
38
39unsigned long get_board_ddr_clk(void)
40{
41 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
42
43 switch (ddrclk_conf & 0x03) {
44 case QIXIS_CLK_100:
45 return 100000000;
46 case QIXIS_CLK_125:
47 return 125000000;
48 case QIXIS_CLK_133:
49 return 133333333;
50 }
51 return 66666666;
52}
53
54void board_init_f(ulong bootflag)
55{
56 u32 plat_ratio, sys_clk, uart_clk;
57 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
58
59 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
60 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
61
62 /* Update GD pointer */
63 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
64
65 /* compiler optimization barrier needed for GCC >= 3.4 */
66 __asm__ __volatile__("" : : : "memory");
67
68 console_init_f();
69
70 /* initialize selected port with appropriate baud rate */
71 sys_clk = get_board_sys_clk();
72 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
73 uart_clk = sys_clk * plat_ratio / 2;
74
75 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
76 uart_clk / 16 / CONFIG_BAUDRATE);
77
78 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
79}
80
81void board_init_r(gd_t *gd, ulong dest_addr)
82{
83 bd_t *bd;
84
85 bd = (bd_t *)(gd + sizeof(gd_t));
86 memset(bd, 0, sizeof(bd_t));
87 gd->bd = bd;
88 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
89 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
90
Simon Glass302445a2017-01-23 13:31:22 -070091 arch_cpu_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053092 get_clocks();
93 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
94 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040095 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053096
97#ifndef CONFIG_SPL_NAND_BOOT
98 env_init();
99 env_relocate();
100#else
101 /* relocate environment function pointers etc. */
102 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500103 (uchar *)SPL_ENV_ADDR);
104 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -0600105 gd->env_valid = ENV_VALID;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530106#endif
107
108 i2c_init_all();
109
110 puts("\n\n");
111
Simon Glassd35f3382017-04-06 12:47:05 -0600112 dram_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530113
114#ifdef CONFIG_SPL_NAND_BOOT
115 nand_boot();
116#endif
117}