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git01.mediatek.com / filogic / uboot / 60af21bcc3f257239c2e4b6c6e4db9c023ac7658 / . / arch / arm / dts / socfpga_agilex5-u-boot.dtsi
blob: 4270dce38dfb50f7fbaad603d4a0ecd21a019f5c [file] [log] [blame]
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * U-Boot additions
4 *
5 * Copyright (C) 2024 Intel Corporation <www.intel.com>
Tien Fong Chee60af21b2025-02-18 16:34:54 +0800[diff] [blame^]6 * Copyright (C) 2025 Altera Corporation <www.altera.com>
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]7 */
8
9#include "socfpga_soc64_fit-u-boot.dtsi"
10
11/{
12 memory {
13 #address-cells = <2>;
14 #size-cells = <2>;
15 bootph-all;
16 };
Tien Fong Chee60af21b2025-02-18 16:34:54 +0800[diff] [blame^]17
18 soc {
19 bootph-all;
20
21 socfpga_ccu_config: socfpga-ccu-config {
22 compatible = "intel,socfpga-dtreg";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 bootph-all;
26
27 /* DSU */
28 i_ccu_caiu0@1c000000 {
29 reg = <0x1c000000 0x00001000>;
30 intel,offset-settings =
31 /* CAIUMIFSR */
32 <0x000003c4 0x00000000 0x07070777>,
33 /* DII1_MPFEREGS */
34 <0x00000414 0x00018000 0xffffffff>,
35 <0x00000418 0x00000000 0x000000ff>,
36 <0x00000410 0xc0e00200 0xc1f03e1f>,
37 /* DII2_GICREGS */
38 <0x00000424 0x0001d000 0xffffffff>,
39 <0x00000428 0x00000000 0x000000ff>,
40 <0x00000420 0xc0800400 0xc1f03e1f>,
41 /* NCAIU0_LWSOC2FPGA */
42 <0x00000444 0x00020000 0xffffffff>,
43 <0x00000448 0x00000000 0x000000ff>,
44 <0x00000440 0xc1100006 0xc1f03e1f>,
45 /* NCAIU0_SOC2FPGA_1G */
46 <0x00000454 0x00040000 0xffffffff>,
47 <0x00000458 0x00000000 0x000000ff>,
48 <0x00000450 0xc1200006 0xc1f03e1f>,
49 /* DMI_SDRAM_2G */
50 <0x00000464 0x00080000 0xffffffff>,
51 <0x00000468 0x00000000 0x000000ff>,
52 /* NCAIU0_SOC2FPGA_16G */
53 <0x00000474 0x00400000 0xffffffff>,
54 <0x00000478 0x00000000 0x000000ff>,
55 <0x00000470 0xc1600006 0xc1f03e1f>,
56 /* DMI_SDRAM_30G */
57 <0x00000484 0x00800000 0xffffffff>,
58 <0x00000488 0x00000000 0x000000ff>,
59 /* NCAIU0_SOC2FPGA_256G */
60 <0x00000494 0x04000000 0xffffffff>,
61 <0x00000498 0x00000000 0x000000ff>,
62 <0x00000490 0xc1a00006 0xc1f03e1f>,
63 /* DMI_SDRAM_480G */
64 <0x000004a4 0x08000000 0xffffffff>,
65 <0x000004a8 0x00000000 0x000000ff>;
66 bootph-all;
67 };
68
69 /* FPGA2SOC */
70 i_ccu_ncaiu0@1c001000 {
71 reg = <0x1c001000 0x00001000>;
72 intel,offset-settings =
73 /* NCAIU0MIFSR */
74 <0x000003c4 0x00000000 0x07070777>,
75 /* PSS */
76 <0x00000404 0x00010000 0xffffffff>,
77 <0x00000408 0x00000000 0x000000ff>,
78 <0x00000400 0xC0F00000 0xc1f03e1f>,
79 /* DII1_MPFEREGS */
80 <0x00000414 0x00018000 0xffffffff>,
81 <0x00000418 0x00000000 0x000000ff>,
82 <0x00000410 0xc0e00200 0xc1f03e1f>,
83 /* NCAIU0_LWSOC2FPGA */
84 <0x00000444 0x00020000 0xffffffff>,
85 <0x00000448 0x00000000 0x000000ff>,
86 <0x00000440 0xc1100006 0xc1f03e1f>,
87 /* NCAIU0_SOC2FPGA_1G */
88 <0x00000454 0x00040000 0xffffffff>,
89 <0x00000458 0x00000000 0x000000ff>,
90 <0x00000450 0xc1200006 0xc1f03e1f>,
91 /* DMI_SDRAM_2G */
92 <0x00000464 0x00080000 0xffffffff>,
93 <0x00000468 0x00000000 0x000000ff>,
94 /* NCAIU0_SOC2FPGA_16G */
95 <0x00000474 0x00400000 0xffffffff>,
96 <0x00000478 0x00000000 0x000000ff>,
97 <0x00000470 0xc1600006 0xc1f03e1f>,
98 /* DMI_SDRAM_30G */
99 <0x00000484 0x00800000 0xffffffff>,
100 <0x00000488 0x00000000 0x000000ff>,
101 /* NCAIU0_SOC2FPGA_256G */
102 <0x00000494 0x04000000 0xffffffff>,
103 <0x00000498 0x00000000 0x000000ff>,
104 <0x00000490 0xc1a00006 0xc1f03e1f>,
105 /* DMI_SDRAM_480G */
106 <0x000004a4 0x08000000 0xffffffff>,
107 <0x000004a8 0x00000000 0x000000ff>;
108 bootph-all;
109 };
110
111 /* GIC_M */
112 i_ccu_ncaiu1@1c002000 {
113 reg = <0x1c002000 0x00001000>;
114 intel,offset-settings =
115 /* NCAIU1MIFSR */
116 <0x000003c4 0x00000000 0x07070777>,
117 /* DMI_SDRAM_2G */
118 <0x00000464 0x00080000 0xffffffff>,
119 <0x00000468 0x00000000 0x000000ff>,
120 /* DMI_SDRAM_30G */
121 <0x00000484 0x00800000 0xffffffff>,
122 <0x00000488 0x00000000 0x000000ff>,
123 /* DMI_SDRAM_480G */
124 <0x000004a4 0x08000000 0xffffffff>,
125 <0x000004a8 0x00000000 0x000000ff>;
126 bootph-all;
127 };
128
129 /* SMMU */
130 i_ccu_ncaiu2@1c003000 {
131 reg = <0x1c003000 0x00001000>;
132 intel,offset-settings =
133 /* NCAIU2MIFSR */
134 <0x000003c4 0x00000000 0x07070777>,
135 /* DMI_SDRAM_2G */
136 <0x00000464 0x00080000 0xffffffff>,
137 <0x00000468 0x00000000 0x000000ff>,
138 /* DMI_SDRAM_30G */
139 <0x00000484 0x00800000 0xffffffff>,
140 <0x00000488 0x00000000 0x000000ff>,
141 /* DMI_SDRAM_480G */
142 <0x000004a4 0x08000000 0xffffffff>,
143 <0x000004a8 0x00000000 0x000000ff>;
144 bootph-all;
145 };
146
147 /* PSS NOC */
148 i_ccu_ncaiu3@1c004000 {
149 reg = <0x1c004000 0x00001000>;
150 intel,offset-settings =
151 /* NCAIU3MIFSR */
152 <0x000003c4 0x00000000 0x07070777>,
153 /* DII1_MPFEREGS */
154 <0x00000414 0x00018000 0xffffffff>,
155 <0x00000418 0x00000000 0x000000ff>,
156 <0x00000410 0xc0e00200 0xc1f03e1f>,
157 /* DMI_SDRAM_2G */
158 <0x00000464 0x00080000 0xffffffff>,
159 <0x00000468 0x00000000 0x000000ff>,
160 /* DMI_SDRAM_30G */
161 <0x00000484 0x00800000 0xffffffff>,
162 <0x00000488 0x00000000 0x000000ff>,
163 /* DMI_SDRAM_480G */
164 <0x000004a4 0x08000000 0xffffffff>,
165 <0x000004a8 0x00000000 0x000000ff>;
166 bootph-all;
167 };
168
169 /* DCE0 */
170 i_ccu_dce0@1c005000 {
171 reg = <0x1c005000 0x00001000>;
172 intel,offset-settings =
173 /* DCEUMIFSR0 */
174 <0x000003c4 0x00000000 0x07070777>,
175 /* DMI_SDRAM_2G */
176 <0x00000464 0x00080000 0xffffffff>,
177 <0x00000468 0x00000000 0x000000ff>,
178 /* DMI_SDRAM_30G */
179 <0x00000484 0x00800000 0xffffffff>,
180 <0x00000488 0x00000000 0x000000ff>,
181 /* DMI_SDRAM_480G */
182 <0x000004a4 0x08000000 0xffffffff>,
183 <0x000004a8 0x00000000 0x000000ff>;
184 bootph-all;
185 };
186
187 /* DCE1 */
188 i_ccu_dce1@1c006000 {
189 reg = <0x1c006000 0x00001000>;
190 intel,offset-settings =
191 /* DCEUMIFSR1 */
192 <0x000003c4 0x00000000 0x07070777>,
193 /* DMI_SDRAM_2G */
194 <0x00000464 0x00080000 0xffffffff>,
195 <0x00000468 0x00000000 0x000000ff>,
196 /* DMI_SDRAM_30G */
197 <0x00000484 0x00800000 0xffffffff>,
198 <0x00000488 0x00000000 0x000000ff>,
199 /* DMI_SDRAM_480G */
200 <0x000004a4 0x08000000 0xffffffff>,
201 <0x000004a8 0x00000000 0x000000ff>;
202 bootph-all;
203 };
204
205 /* DMI0 */
206 i_ccu_dmi0@1c007000 {
207 reg = <0x1c007000 0x00001000>;
208 intel,offset-settings =
209 /* DMIUSMCTCR */
210 <0x00000300 0x00000001 0x00000003>,
211 <0x00000300 0x00000003 0x00000003>;
212 bootph-all;
213 };
214
215 /* DMI1 */
216 i_ccu_dmi0@1c008000 {
217 reg = <0x1c008000 0x00001000>;
218 intel,offset-settings =
219 /* DMIUSMCTCR */
220 <0x00000300 0x00000001 0x00000003>,
221 <0x00000300 0x00000003 0x00000003>;
222 bootph-all;
223 };
224 };
225 };
Jit Loon Lim977071e2024-03-12 22:01:03 +0800[diff] [blame]226};
227
228&clkmgr {
229 bootph-all;
230};
231
232&i2c0 {
233 reset-names = "i2c";
234};
235
236&i2c1 {
237 reset-names = "i2c";
238};
239
240&i2c2 {
241 reset-names = "i2c";
242};
243
244&i2c3 {
245 reset-names = "i2c";
246};
247
248&mmc {
249 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
250};
251
252&porta {
253 bank-name = "porta";
254};
255
256&portb {
257 bank-name = "portb";
258};
259
260&qspi {
261 bootph-all;
262};
263
264&rst {
265 compatible = "altr,rst-mgr";
266 altr,modrst-offset = <0x24>;
267 bootph-all;
268};
269
270&sysmgr {
271 compatible = "altr,sys-mgr", "syscon";
272 bootph-all;
273};
274
275&uart0 {
276 bootph-all;
277};
278
279&watchdog0 {
280 bootph-all;
281};