| Simon Glass | 30580fc | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Google, Inc |
| 3 | * |
| 4 | * From Coreboot file of the same name |
| 5 | * |
| 6 | * Copyright (C) 2007-2008 coresystems GmbH |
| 7 | * Copyright (C) 2011 Google Inc. |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0 |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ACH_ASM_SANDYBRIDGE_H |
| 13 | #define _ACH_ASM_SANDYBRIDGE_H |
| 14 | |
| 15 | /* Chipset types */ |
| 16 | #define SANDYBRIDGE_MOBILE 0 |
| 17 | #define SANDYBRIDGE_DESKTOP 1 |
| 18 | #define SANDYBRIDGE_SERVER 2 |
| 19 | |
| 20 | /* Device ID for SandyBridge and IvyBridge */ |
| 21 | #define BASE_REV_SNB 0x00 |
| 22 | #define BASE_REV_IVB 0x50 |
| 23 | #define BASE_REV_MASK 0x50 |
| 24 | |
| 25 | /* SandyBridge CPU stepping */ |
| 26 | #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ |
| 27 | #define SNB_STEP_D1 (BASE_REV_SNB + 6) |
| 28 | #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ |
| 29 | |
| 30 | /* IvyBridge CPU stepping */ |
| 31 | #define IVB_STEP_A0 (BASE_REV_IVB + 0) |
| 32 | #define IVB_STEP_B0 (BASE_REV_IVB + 2) |
| 33 | #define IVB_STEP_C0 (BASE_REV_IVB + 4) |
| 34 | #define IVB_STEP_K0 (BASE_REV_IVB + 5) |
| 35 | #define IVB_STEP_D0 (BASE_REV_IVB + 6) |
| 36 | |
| 37 | /* Intel Enhanced Debug region must be 4MB */ |
| 38 | #define IED_SIZE 0x400000 |
| 39 | |
| 40 | /* Northbridge BARs */ |
| 41 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 42 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
| 43 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
| 44 | #define DEFAULT_RCBABASE 0xfed1c000 |
| 45 | /* 4 KB per PCIe device */ |
| 46 | #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS |
| 47 | |
| 48 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 49 | #define EPBAR 0x40 |
| 50 | #define MCHBAR 0x48 |
| 51 | #define PCIEXBAR 0x60 |
| 52 | #define DMIBAR 0x68 |
| 53 | #define X60BAR 0x60 |
| 54 | |
| 55 | #define GGC 0x50 /* GMCH Graphics Control */ |
| 56 | |
| 57 | #define DEVEN 0x54 /* Device Enable */ |
| 58 | #define DEVEN_PEG60 (1 << 13) |
| 59 | #define DEVEN_IGD (1 << 4) |
| 60 | #define DEVEN_PEG10 (1 << 3) |
| 61 | #define DEVEN_PEG11 (1 << 2) |
| 62 | #define DEVEN_PEG12 (1 << 1) |
| 63 | #define DEVEN_HOST (1 << 0) |
| 64 | |
| 65 | #define PAM0 0x80 |
| 66 | #define PAM1 0x81 |
| 67 | #define PAM2 0x82 |
| 68 | #define PAM3 0x83 |
| 69 | #define PAM4 0x84 |
| 70 | #define PAM5 0x85 |
| 71 | #define PAM6 0x86 |
| 72 | |
| 73 | #define LAC 0x87 /* Legacy Access Control */ |
| 74 | #define SMRAM 0x88 /* System Management RAM Control */ |
| 75 | #define D_OPEN (1 << 6) |
| 76 | #define D_CLS (1 << 5) |
| 77 | #define D_LCK (1 << 4) |
| 78 | #define G_SMRAME (1 << 3) |
| 79 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 80 | |
| 81 | #define TOM 0xa0 |
| 82 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
| 83 | #define TSEG 0xb8 /* TSEG base */ |
| 84 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 85 | |
| 86 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 87 | |
| 88 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 89 | #define BCTRL1 0x3e /* 16bit */ |
| 90 | |
| 91 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 92 | |
| 93 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
| 94 | #define SWSCI 0xe8 /* SWSCI enable */ |
| 95 | #define ASLS 0xfc /* OpRegion Base */ |
| 96 | |
| 97 | /* |
| 98 | * MCHBAR |
| 99 | */ |
| 100 | #define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg)) |
| 101 | |
| 102 | #define SSKPD 0x5d14 /* 16bit (scratchpad) */ |
| 103 | #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |
| 104 | |
| 105 | void sandybridge_early_init(int chipset_type); |
| 106 | |
| 107 | #endif |