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git01.mediatek.com / filogic / uboot / 60a9f713ebb86465e706d0be032fe812727aa4f8 / . / arch / arm / mach-socfpga / wrap_pll_config.c
blob: 0c40ae987613ac30af29e3b491e0349b6cefdc32 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]2/*
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]4 */
5
6#include <common.h>
7#include <asm/arch/clock_manager.h>
Marek Vasutaefb78d2015-08-02 21:12:09 +0200[diff] [blame]8#include <qts/pll_config.h>
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]9
10#define MAIN_VCO_BASE ( \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]11 (CFG_HPS_MAINPLLGRP_VCO_DENOM << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]12 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]13 (CFG_HPS_MAINPLLGRP_VCO_NUMER << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]14 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
15 )
16
17#define PERI_VCO_BASE ( \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]18 (CFG_HPS_PERPLLGRP_VCO_PSRC << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]19 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]20 (CFG_HPS_PERPLLGRP_VCO_DENOM << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]21 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]22 (CFG_HPS_PERPLLGRP_VCO_NUMER << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]23 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
24 )
25
26#define SDR_VCO_BASE ( \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]27 (CFG_HPS_SDRPLLGRP_VCO_SSRC << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]28 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]29 (CFG_HPS_SDRPLLGRP_VCO_DENOM << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]30 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]31 (CFG_HPS_SDRPLLGRP_VCO_NUMER << \
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]32 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
33 )
34
35static const struct cm_config cm_default_cfg = {
36 /* main group */
37 MAIN_VCO_BASE,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]38 (CFG_HPS_MAINPLLGRP_MPUCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]39 CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]40 (CFG_HPS_MAINPLLGRP_MAINCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]41 CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]42 (CFG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]43 CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]44 (CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]45 CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]46 (CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]47 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]48 (CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]49 CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]50 (CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]51 CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]52 (CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]53 CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]54 (CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]55 CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]56 (CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]57 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]58 (CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]59 CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]60 (CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]61 CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]62 (CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]63 CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]64 (CFG_HPS_MAINPLLGRP_L4SRC_L4MP <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]65 CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]66 (CFG_HPS_MAINPLLGRP_L4SRC_L4SP <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]67 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
68
69 /* peripheral group */
70 PERI_VCO_BASE,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]71 (CFG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]72 CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]73 (CFG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]74 CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]75 (CFG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]76 CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]77 (CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]78 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]79 (CFG_HPS_PERPLLGRP_PERBASECLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]80 CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]81 (CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]82 CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]83 (CFG_HPS_PERPLLGRP_DIV_USBCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]84 CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]85 (CFG_HPS_PERPLLGRP_DIV_SPIMCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]86 CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]87 (CFG_HPS_PERPLLGRP_DIV_CAN0CLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]88 CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]89 (CFG_HPS_PERPLLGRP_DIV_CAN1CLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]90 CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]91 (CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]92 CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]93 (CFG_HPS_PERPLLGRP_SRC_QSPI <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]94 CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]95 (CFG_HPS_PERPLLGRP_SRC_NAND <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]96 CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]97 (CFG_HPS_PERPLLGRP_SRC_SDMMC <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]98 CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
99
100 /* sdram pll group */
101 SDR_VCO_BASE,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]102 (CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]103 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]104 (CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]105 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]106 (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]107 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]108 (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]109 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]110 (CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]111 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]112 (CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]113 CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]114 (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]115 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]116 (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]117 CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
Dinh Nguyen2492b9f2017-01-31 12:33:08 -0600[diff] [blame]118
119 /* altera group */
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]120 CFG_HPS_ALTERAGRP_MPUCLK,
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]121};
122
123const struct cm_config * const cm_get_default_config(void)
124{
125 return &cm_default_cfg;
126}
127
128const unsigned int cm_get_osc_clk_hz(const int osc)
129{
130 if (osc == 1)
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]131 return CFG_HPS_CLK_OSC1_HZ;
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]132 else if (osc == 2)
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]133 return CFG_HPS_CLK_OSC2_HZ;
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]134 else
135 return 0;
136}
137
138const unsigned int cm_get_f2s_per_ref_clk_hz(void)
139{
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]140 return CFG_HPS_CLK_F2S_PER_REF_HZ;
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]141}
142
143const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
144{
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]145 return CFG_HPS_CLK_F2S_SDR_REF_HZ;
Marek Vasut084d06c2015-07-25 08:44:27 +0200[diff] [blame]146}