blob: dc30bdf3e5c28cbd489a4d0e5da3b31821b4e070 [file] [log] [blame]
Paul Barkera774a3e2023-10-16 10:25:27 +01001# Copyright (C) 2023 Renesas Electronics Corporation
2# SPDX-License-Identifier: GPL-2.0+
3
4if RZG2L
5
Paul Barkera07d3132023-10-16 10:25:28 +01006config R9A07G044L
7 bool "Renesas R9A07G044L SoC"
Paul Barker132d7ea2023-10-16 10:25:29 +01008 imply CLK_R9A07G044
Paul Barkera07d3132023-10-16 10:25:28 +01009 help
10 Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
11
Paul Barker60a0b942023-10-16 10:25:43 +010012choice
13 prompt "Renesas RZ/G2L Family Board selection"
14 default TARGET_RZG2L_SMARC_EVK
15
16config TARGET_RZG2L_SMARC_EVK
17 bool "Renesas RZ/G2L SMARC EVK"
18 imply R9A07G044L
19 help
20 Enable support for the RZ/G2L SMARC evaluation board.
21
22source "board/renesas/rzg2l/Kconfig"
23
24endchoice
25
Paul Barkera774a3e2023-10-16 10:25:27 +010026config MULTI_DTB_FIT_UNCOMPRESS_SZ
27 default 0x80000 if TARGET_RZG2L_SMARC_EVK
28
29config MULTI_DTB_FIT_USER_DEF_ADDR
30 default 0x49000000 if TARGET_RZG2L_SMARC_EVK
31
32endif