Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Patrice Chotard | 8e22927 | 2018-02-09 13:09:54 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
| 4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
Patrice Chotard | 8e22927 | 2018-02-09 13:09:54 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _GPIO_H_ |
| 8 | #define _GPIO_H_ |
| 9 | |
Patrice Chotard | 20ddb32 | 2018-12-03 10:52:52 +0100 | [diff] [blame] | 10 | #define STM32_GPIOS_PER_BANK 16 |
| 11 | |
Patrice Chotard | 8e22927 | 2018-02-09 13:09:54 +0100 | [diff] [blame] | 12 | enum stm32_gpio_port { |
| 13 | STM32_GPIO_PORT_A = 0, |
| 14 | STM32_GPIO_PORT_B, |
| 15 | STM32_GPIO_PORT_C, |
| 16 | STM32_GPIO_PORT_D, |
| 17 | STM32_GPIO_PORT_E, |
| 18 | STM32_GPIO_PORT_F, |
| 19 | STM32_GPIO_PORT_G, |
| 20 | STM32_GPIO_PORT_H, |
| 21 | STM32_GPIO_PORT_I |
| 22 | }; |
| 23 | |
| 24 | enum stm32_gpio_pin { |
| 25 | STM32_GPIO_PIN_0 = 0, |
| 26 | STM32_GPIO_PIN_1, |
| 27 | STM32_GPIO_PIN_2, |
| 28 | STM32_GPIO_PIN_3, |
| 29 | STM32_GPIO_PIN_4, |
| 30 | STM32_GPIO_PIN_5, |
| 31 | STM32_GPIO_PIN_6, |
| 32 | STM32_GPIO_PIN_7, |
| 33 | STM32_GPIO_PIN_8, |
| 34 | STM32_GPIO_PIN_9, |
| 35 | STM32_GPIO_PIN_10, |
| 36 | STM32_GPIO_PIN_11, |
| 37 | STM32_GPIO_PIN_12, |
| 38 | STM32_GPIO_PIN_13, |
| 39 | STM32_GPIO_PIN_14, |
| 40 | STM32_GPIO_PIN_15 |
| 41 | }; |
| 42 | |
| 43 | enum stm32_gpio_mode { |
| 44 | STM32_GPIO_MODE_IN = 0, |
| 45 | STM32_GPIO_MODE_OUT, |
| 46 | STM32_GPIO_MODE_AF, |
| 47 | STM32_GPIO_MODE_AN |
| 48 | }; |
| 49 | |
| 50 | enum stm32_gpio_otype { |
| 51 | STM32_GPIO_OTYPE_PP = 0, |
| 52 | STM32_GPIO_OTYPE_OD |
| 53 | }; |
| 54 | |
| 55 | enum stm32_gpio_speed { |
| 56 | STM32_GPIO_SPEED_2M = 0, |
| 57 | STM32_GPIO_SPEED_25M, |
| 58 | STM32_GPIO_SPEED_50M, |
| 59 | STM32_GPIO_SPEED_100M |
| 60 | }; |
| 61 | |
| 62 | enum stm32_gpio_pupd { |
| 63 | STM32_GPIO_PUPD_NO = 0, |
| 64 | STM32_GPIO_PUPD_UP, |
| 65 | STM32_GPIO_PUPD_DOWN |
| 66 | }; |
| 67 | |
| 68 | enum stm32_gpio_af { |
| 69 | STM32_GPIO_AF0 = 0, |
| 70 | STM32_GPIO_AF1, |
| 71 | STM32_GPIO_AF2, |
| 72 | STM32_GPIO_AF3, |
| 73 | STM32_GPIO_AF4, |
| 74 | STM32_GPIO_AF5, |
| 75 | STM32_GPIO_AF6, |
| 76 | STM32_GPIO_AF7, |
| 77 | STM32_GPIO_AF8, |
| 78 | STM32_GPIO_AF9, |
| 79 | STM32_GPIO_AF10, |
| 80 | STM32_GPIO_AF11, |
| 81 | STM32_GPIO_AF12, |
| 82 | STM32_GPIO_AF13, |
| 83 | STM32_GPIO_AF14, |
| 84 | STM32_GPIO_AF15 |
| 85 | }; |
| 86 | |
| 87 | struct stm32_gpio_dsc { |
| 88 | enum stm32_gpio_port port; |
| 89 | enum stm32_gpio_pin pin; |
| 90 | }; |
| 91 | |
| 92 | struct stm32_gpio_ctl { |
| 93 | enum stm32_gpio_mode mode; |
| 94 | enum stm32_gpio_otype otype; |
| 95 | enum stm32_gpio_speed speed; |
| 96 | enum stm32_gpio_pupd pupd; |
| 97 | enum stm32_gpio_af af; |
| 98 | }; |
| 99 | |
| 100 | struct stm32_gpio_regs { |
| 101 | u32 moder; /* GPIO port mode */ |
| 102 | u32 otyper; /* GPIO port output type */ |
| 103 | u32 ospeedr; /* GPIO port output speed */ |
| 104 | u32 pupdr; /* GPIO port pull-up/pull-down */ |
| 105 | u32 idr; /* GPIO port input data */ |
| 106 | u32 odr; /* GPIO port output data */ |
| 107 | u32 bsrr; /* GPIO port bit set/reset */ |
| 108 | u32 lckr; /* GPIO port configuration lock */ |
| 109 | u32 afr[2]; /* GPIO alternate function */ |
| 110 | }; |
| 111 | |
| 112 | struct stm32_gpio_priv { |
| 113 | struct stm32_gpio_regs *regs; |
Patrice Chotard | 0099c1e | 2018-12-03 10:52:51 +0100 | [diff] [blame] | 114 | unsigned int gpio_range; |
Patrice Chotard | 8e22927 | 2018-02-09 13:09:54 +0100 | [diff] [blame] | 115 | }; |
| 116 | |
Patrice Chotard | 0099c1e | 2018-12-03 10:52:51 +0100 | [diff] [blame] | 117 | int stm32_offset_to_index(struct udevice *dev, unsigned int offset); |
| 118 | |
Patrice Chotard | 8e22927 | 2018-02-09 13:09:54 +0100 | [diff] [blame] | 119 | #endif /* _GPIO_H_ */ |