blob: 95d6156476f4494affea3897b665ab6c77a83700 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
Yangbo Lu49dd6e42019-05-23 11:05:45 +08004 * Copyright 2019 NXP Semiconductors
Mingkai Hu0e58b512015-10-26 19:47:50 +08005 *
Mingkai Hu0e58b512015-10-26 19:47:50 +08006 */
7
8#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
9#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
10
11#include <common.h>
12
13enum mxc_clock {
14 MXC_ARM_CLK = 0,
15 MXC_BUS_CLK,
16 MXC_UART_CLK,
Mingkai Hu0e58b512015-10-26 19:47:50 +080017 MXC_I2C_CLK,
18 MXC_DSPI_CLK,
19};
20
21unsigned int mxc_get_clock(enum mxc_clock clk);
Simon Glass243182c2017-05-17 08:23:06 -060022ulong get_ddr_freq(ulong);
23uint get_svr(void);
Mingkai Hu0e58b512015-10-26 19:47:50 +080024
25#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */