blob: 956f8a1eb2fde0e66c9b6619a7fedf399882ce3a [file] [log] [blame]
Ye Li0db17f42021-08-07 16:00:41 +08001// SPDX-License-Identifier: GPL-2.0
2/*
Ye Lic408ed32022-07-26 16:40:49 +08003 * Copyright 2020-2022 NXP
Ye Li0db17f42021-08-07 16:00:41 +08004 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <dm.h>
9#include <dm/lists.h>
10#include <dm/root.h>
11#include <dm/device-internal.h>
Peng Fand5c31832023-06-15 18:09:05 +080012#include <asm/mach-imx/ele_api.h>
Peng Fanf6928f92021-08-07 16:01:09 +080013#include <asm/arch/imx-regs.h>
Ye Li0db17f42021-08-07 16:00:41 +080014#include <linux/iopoll.h>
15#include <misc.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Ye Li0db17f42021-08-07 16:00:41 +080019struct imx8ulp_mu {
20 struct mu_type *base;
21};
22
23#define MU_SR_TE0_MASK BIT(0)
24#define MU_SR_RF0_MASK BIT(0)
Ye Li606fbf42023-06-15 18:09:12 +080025#define MU_TR_COUNT 8
Ye Li0db17f42021-08-07 16:00:41 +080026#define MU_RR_COUNT 4
27
Ye Li853cc9d2021-08-07 16:00:55 +080028void mu_hal_init(ulong base)
Ye Li0db17f42021-08-07 16:00:41 +080029{
Ye Li853cc9d2021-08-07 16:00:55 +080030 struct mu_type *mu_base = (struct mu_type *)base;
31
32 writel(0, &mu_base->tcr);
33 writel(0, &mu_base->rcr);
Ye Li0db17f42021-08-07 16:00:41 +080034}
35
Ye Li853cc9d2021-08-07 16:00:55 +080036int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
Ye Li0db17f42021-08-07 16:00:41 +080037{
Ye Li853cc9d2021-08-07 16:00:55 +080038 struct mu_type *mu_base = (struct mu_type *)base;
Ye Li0db17f42021-08-07 16:00:41 +080039 u32 mask = MU_SR_TE0_MASK << reg_index;
40 u32 val;
41 int ret;
42
43 assert(reg_index < MU_TR_COUNT);
44
Ye Li853cc9d2021-08-07 16:00:55 +080045 debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
Ye Li0db17f42021-08-07 16:00:41 +080046
47 /* Wait TX register to be empty. */
Ye Li853cc9d2021-08-07 16:00:55 +080048 ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
Ye Li0db17f42021-08-07 16:00:41 +080049 if (ret < 0) {
50 debug("%s timeout\n", __func__);
51 return -ETIMEDOUT;
52 }
53
54 debug("tr[%d] 0x%x\n", reg_index, msg);
55
Ye Li853cc9d2021-08-07 16:00:55 +080056 writel(msg, &mu_base->tr[reg_index]);
Ye Li0db17f42021-08-07 16:00:41 +080057
58 return 0;
59}
60
Ye Li853cc9d2021-08-07 16:00:55 +080061int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
Ye Li0db17f42021-08-07 16:00:41 +080062{
Ye Li853cc9d2021-08-07 16:00:55 +080063 struct mu_type *mu_base = (struct mu_type *)base;
Ye Li0db17f42021-08-07 16:00:41 +080064 u32 mask = MU_SR_RF0_MASK << reg_index;
65 u32 val;
66 int ret;
67
Ye Li606fbf42023-06-15 18:09:12 +080068 assert(reg_index < MU_RR_COUNT);
Ye Li0db17f42021-08-07 16:00:41 +080069
Ye Li853cc9d2021-08-07 16:00:55 +080070 debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
Ye Li0db17f42021-08-07 16:00:41 +080071
72 /* Wait RX register to be full. */
Ye Li853cc9d2021-08-07 16:00:55 +080073 ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
Ye Li0db17f42021-08-07 16:00:41 +080074 if (ret < 0) {
75 debug("%s timeout\n", __func__);
76 return -ETIMEDOUT;
77 }
78
Ye Li853cc9d2021-08-07 16:00:55 +080079 *msg = readl(&mu_base->rr[reg_index]);
Ye Li0db17f42021-08-07 16:00:41 +080080
81 debug("rr[%d] 0x%x\n", reg_index, *msg);
82
83 return 0;
84}
85
86static int imx8ulp_mu_read(struct mu_type *base, void *data)
87{
Peng Fand5c31832023-06-15 18:09:05 +080088 struct ele_msg *msg = (struct ele_msg *)data;
Ye Li0db17f42021-08-07 16:00:41 +080089 int ret;
90 u8 count = 0;
91
92 if (!msg)
93 return -EINVAL;
94
95 /* Read first word */
Ye Li853cc9d2021-08-07 16:00:55 +080096 ret = mu_hal_receivemsg((ulong)base, 0, (u32 *)msg);
Ye Li0db17f42021-08-07 16:00:41 +080097 if (ret)
98 return ret;
99 count++;
100
101 /* Check size */
Peng Fand5c31832023-06-15 18:09:05 +0800102 if (msg->size > ELE_MAX_MSG) {
Ye Li0db17f42021-08-07 16:00:41 +0800103 *((u32 *)msg) = 0;
104 return -EINVAL;
105 }
106
107 /* Read remaining words */
108 while (count < msg->size) {
Ye Li853cc9d2021-08-07 16:00:55 +0800109 ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
Ye Li0db17f42021-08-07 16:00:41 +0800110 &msg->data[count - 1]);
111 if (ret)
112 return ret;
113 count++;
114 }
115
116 return 0;
117}
118
119static int imx8ulp_mu_write(struct mu_type *base, void *data)
120{
Peng Fand5c31832023-06-15 18:09:05 +0800121 struct ele_msg *msg = (struct ele_msg *)data;
Ye Li0db17f42021-08-07 16:00:41 +0800122 int ret;
123 u8 count = 0;
124
125 if (!msg)
126 return -EINVAL;
127
128 /* Check size */
Peng Fand5c31832023-06-15 18:09:05 +0800129 if (msg->size > ELE_MAX_MSG)
Ye Li0db17f42021-08-07 16:00:41 +0800130 return -EINVAL;
131
132 /* Write first word */
Ye Li853cc9d2021-08-07 16:00:55 +0800133 ret = mu_hal_sendmsg((ulong)base, 0, *((u32 *)msg));
Ye Li0db17f42021-08-07 16:00:41 +0800134 if (ret)
135 return ret;
136 count++;
137
138 /* Write remaining words */
139 while (count < msg->size) {
Ye Li853cc9d2021-08-07 16:00:55 +0800140 ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
Ye Li0db17f42021-08-07 16:00:41 +0800141 msg->data[count - 1]);
142 if (ret)
143 return ret;
144 count++;
145 }
146
147 return 0;
148}
149
150/*
151 * Note the function prototype use msgid as the 2nd parameter, here
152 * we take it as no_resp.
153 */
154static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
155 int tx_size, void *rx_msg, int rx_size)
156{
157 struct imx8ulp_mu *priv = dev_get_priv(dev);
158 u32 result;
159 int ret;
160
161 /* Expect tx_msg, rx_msg are the same value */
162 if (rx_msg && tx_msg != rx_msg)
163 printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
164
165 ret = imx8ulp_mu_write(priv->base, tx_msg);
166 if (ret)
167 return ret;
168 if (!no_resp) {
169 ret = imx8ulp_mu_read(priv->base, rx_msg);
170 if (ret)
171 return ret;
172 }
173
Peng Fand5c31832023-06-15 18:09:05 +0800174 result = ((struct ele_msg *)rx_msg)->data[0];
Ye Li79581a62021-08-07 16:00:51 +0800175 if ((result & 0xff) == 0xd6)
Ye Li0db17f42021-08-07 16:00:41 +0800176 return 0;
177
178 return -EIO;
179}
180
181static int imx8ulp_mu_probe(struct udevice *dev)
182{
183 struct imx8ulp_mu *priv = dev_get_priv(dev);
184 fdt_addr_t addr;
185
186 debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
187
188 addr = devfdt_get_addr(dev);
189 if (addr == FDT_ADDR_T_NONE)
190 return -EINVAL;
191
192 priv->base = (struct mu_type *)addr;
193
194 debug("mu base 0x%lx\n", (ulong)priv->base);
195
196 /* U-Boot not enable interrupts, so need to enable RX interrupts */
Ye Li853cc9d2021-08-07 16:00:55 +0800197 mu_hal_init((ulong)priv->base);
Ye Li0db17f42021-08-07 16:00:41 +0800198
Peng Fand5c31832023-06-15 18:09:05 +0800199 gd->arch.ele_dev = dev;
Ye Li0db17f42021-08-07 16:00:41 +0800200
201 return 0;
202}
203
204static int imx8ulp_mu_remove(struct udevice *dev)
205{
206 return 0;
207}
208
209static int imx8ulp_mu_bind(struct udevice *dev)
210{
211 debug("%s(dev=%p)\n", __func__, dev);
212
213 return 0;
214}
215
216static struct misc_ops imx8ulp_mu_ops = {
217 .call = imx8ulp_mu_call,
218};
219
220static const struct udevice_id imx8ulp_mu_ids[] = {
221 { .compatible = "fsl,imx8ulp-mu" },
Peng Fan1e9aff12022-07-26 16:40:50 +0800222 { .compatible = "fsl,imx93-mu-s4" },
Ye Li0db17f42021-08-07 16:00:41 +0800223 { }
224};
225
226U_BOOT_DRIVER(imx8ulp_mu) = {
227 .name = "imx8ulp_mu",
228 .id = UCLASS_MISC,
229 .of_match = imx8ulp_mu_ids,
230 .probe = imx8ulp_mu_probe,
231 .bind = imx8ulp_mu_bind,
232 .remove = imx8ulp_mu_remove,
233 .ops = &imx8ulp_mu_ops,
234 .priv_auto = sizeof(struct imx8ulp_mu),
235};