blob: 292802f4c0fec4787baa40dcf688fb1de512be04 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jon Masond59b5862017-03-17 12:12:14 -04002/*
3 * (C) Copyright 2016 Broadcom Ltd.
Jon Masond59b5862017-03-17 12:12:14 -04004 */
5#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07006#include <cpu_func.h>
Jon Masond59b5862017-03-17 12:12:14 -04007#include <asm/system.h>
8#include <asm/armv8/mmu.h>
9
10static struct mm_region ns2_mem_map[] = {
11 {
12 .virt = 0x0UL,
13 .phys = 0x0UL,
14 .size = 0x80000000UL,
15 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
16 PTE_BLOCK_NON_SHARE |
17 PTE_BLOCK_PXN | PTE_BLOCK_UXN
18 }, {
19 .virt = 0x80000000UL,
20 .phys = 0x80000000UL,
21 .size = 0xff80000000UL,
22 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
23 PTE_BLOCK_INNER_SHARE
24 }, {
25 /* List terminator */
26 0,
27 }
28};
29
30struct mm_region *mem_map = ns2_mem_map;
31
32DECLARE_GLOBAL_DATA_PTR;
33
34int board_init(void)
35{
36 return 0;
37}
38
39int dram_init(void)
40{
41 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
42 PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
43 return 0;
44}
45
Simon Glass2f949c32017-03-31 08:40:32 -060046int dram_init_banksize(void)
Jon Masond59b5862017-03-17 12:12:14 -040047{
48 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
49 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
50
51 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
52 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
Simon Glass2f949c32017-03-31 08:40:32 -060053
54 return 0;
Jon Masond59b5862017-03-17 12:12:14 -040055}
56
57void reset_cpu(ulong addr)
58{
59 psci_system_reset();
60}