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git01.mediatek.com / filogic / uboot / 60649bb39c24dbc7f7889e21cb6d0f713f2cbe5c / . / configs / chromebook_jerry_defconfig
blob: f80faaeff8f086609a75d89ddc9221ef11bb1110 [file] [log] [blame]
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]5# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]6CONFIG_TARGET_CHROMEBOOK_JERRY=y
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]7CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]8CONFIG_SPL_SPI_SUPPORT=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]9CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassba8635d2016-11-13 14:22:10 -0700[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]11CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]12# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]13CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]14# CONFIG_DISPLAY_CPUINFO is not set
Simon Glasse608ced2017-05-31 17:57:33 -0600[diff] [blame]15CONFIG_BOARD_EARLY_INIT_F=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]16CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]17CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]18CONFIG_FASTBOOT_FLASH=y
19CONFIG_FASTBOOT_FLASH_MMC_DEV=0
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]20CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]21CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]22CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]23CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]24CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]25CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]26CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]27CONFIG_CMD_USB=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]28# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]29CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]30CONFIG_CMD_TIME=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]31CONFIG_CMD_PMIC=y
32CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]33# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]34# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]35# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]36CONFIG_SPL_PARTITION_UUIDS=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]37CONFIG_SPL_OF_CONTROL=y
Simon Glass95994612016-11-13 14:22:09 -0700[diff] [blame]38CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]39CONFIG_SPL_OF_PLATDATA=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]40CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]41CONFIG_SPL_REGMAP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]42CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]43CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]44# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]45CONFIG_CLK=y
46CONFIG_SPL_CLK=y
47CONFIG_ROCKCHIP_GPIO=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]48CONFIG_I2C_CROS_EC_TUNNEL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]49CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]50CONFIG_I2C_MUX=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]51CONFIG_DM_KEYBOARD=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]52CONFIG_CROS_EC_KEYB=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]53CONFIG_CROS_EC=y
54CONFIG_CROS_EC_SPI=y
Simon Glassaf0b7442016-01-21 19:43:36 -0700[diff] [blame]55CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]56CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]57CONFIG_MMC_DW_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]58CONFIG_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]59CONFIG_SPL_PINCTRL=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]60# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]61CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]62CONFIG_DM_PMIC=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]63# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]64CONFIG_PMIC_RK8XX=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]65CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]66CONFIG_REGULATOR_RK8XX=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]67CONFIG_PWM_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]68CONFIG_RAM=y
69CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]70CONFIG_DEBUG_UART_BASE=0xff690000
71CONFIG_DEBUG_UART_CLOCK=24000000
72CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]73CONFIG_SYS_NS16550=y
Simon Glass95994612016-11-13 14:22:09 -0700[diff] [blame]74CONFIG_ROCKCHIP_SERIAL=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]75CONFIG_ROCKCHIP_SPI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]76CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]77CONFIG_USB=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]78CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]79CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]80CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
81CONFIG_USB_GADGET_VENDOR_NUM=0x2207
82CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]83CONFIG_USB_GADGET_DWC2_OTG=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]84CONFIG_USB_STORAGE=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]85CONFIG_DM_VIDEO=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]86CONFIG_DISPLAY=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]87CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]88CONFIG_DISPLAY_ROCKCHIP_EDP=y
89CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]90CONFIG_USE_TINY_PRINTF=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]91CONFIG_CMD_DHRYSTONE=y
92CONFIG_ERRNO_STR=y
Simon Glass95994612016-11-13 14:22:09 -0700[diff] [blame]93# CONFIG_SPL_OF_LIBFDT is not set
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]94CONFIG_USB_GADGET_DOWNLOAD=y
95CONFIG_USB_GADGET_VBUS_DRAW=0
96CONFIG_G_DNL_MANUFACTURER="Rockchip"
97CONFIG_G_DNL_VENDOR_NUM=0x2207
98CONFIG_G_DNL_PRODUCT_NUM=0x320a