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git01.mediatek.com / filogic / uboot / 606050d9fb6c26f604249919c31ed87161e79a51 / . / arch / sandbox / dts / test.dts
blob: 4a277934a711383add30ef3b9facec4a0ff24539 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]79 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]84 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]85 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]88 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]89 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]94 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]96 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]97 };
98
99 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]100 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]101 compatible = "not,compatible";
102 };
103
104 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]105 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]106 };
107
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]108 backlight: backlight {
109 compatible = "pwm-backlight";
110 enable-gpios = <&gpio_a 1>;
111 power-supply = <&ldo_1>;
112 pwms = <&pwm 0 1000>;
113 default-brightness-level = <5>;
114 brightness-levels = <0 16 32 64 128 170 202 234 255>;
115 };
116
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]117 bind-test {
118 bind-test-child1 {
119 compatible = "sandbox,phy";
120 #phy-cells = <1>;
121 };
122
123 bind-test-child2 {
124 compatible = "simple-bus";
125 };
126 };
127
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]128 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]129 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]130 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]131 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]132 ping-add = <3>;
133 };
134
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]135 phy_provider0: gen_phy@0 {
136 compatible = "sandbox,phy";
137 #phy-cells = <1>;
138 };
139
140 phy_provider1: gen_phy@1 {
141 compatible = "sandbox,phy";
142 #phy-cells = <0>;
143 broken;
144 };
145
146 gen_phy_user: gen_phy_user {
147 compatible = "simple-bus";
148 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
149 phy-names = "phy1", "phy2", "phy3";
150 };
151
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]152 some-bus {
153 #address-cells = <1>;
154 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]155 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]156 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]157 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]159 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]160 compatible = "denx,u-boot-fdt-test";
161 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]162 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]163 ping-add = <5>;
164 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]165 c-test@0 {
166 compatible = "denx,u-boot-fdt-test";
167 reg = <0>;
168 ping-expect = <6>;
169 ping-add = <6>;
170 };
171 c-test@1 {
172 compatible = "denx,u-boot-fdt-test";
173 reg = <1>;
174 ping-expect = <7>;
175 ping-add = <7>;
176 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]177 };
178
179 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]180 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]181 ping-expect = <6>;
182 ping-add = <6>;
183 compatible = "google,another-fdt-test";
184 };
185
186 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]187 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]188 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]189 ping-add = <6>;
190 compatible = "google,another-fdt-test";
191 };
192
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]193 f-test {
194 compatible = "denx,u-boot-fdt-test";
195 };
196
197 g-test {
198 compatible = "denx,u-boot-fdt-test";
199 };
200
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]201 h-test {
202 compatible = "denx,u-boot-fdt-test1";
203 };
204
Simon Glass204675c2019-12-29 21:19:25 -0700[diff] [blame]205 devres-test {
206 compatible = "denx,u-boot-devres-test";
207 };
208
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]209 clocks {
210 clk_fixed: clk-fixed {
211 compatible = "fixed-clock";
212 #clock-cells = <0>;
213 clock-frequency = <1234>;
214 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]215
216 clk_fixed_factor: clk-fixed-factor {
217 compatible = "fixed-factor-clock";
218 #clock-cells = <0>;
219 clock-div = <3>;
220 clock-mult = <2>;
221 clocks = <&clk_fixed>;
222 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200[diff] [blame]223
224 osc {
225 compatible = "fixed-clock";
226 #clock-cells = <0>;
227 clock-frequency = <20000000>;
228 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]229 };
230
231 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]232 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]233 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]234 assigned-clocks = <&clk_sandbox 3>;
235 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]236 };
237
238 clk-test {
239 compatible = "sandbox,clk-test";
240 clocks = <&clk_fixed>,
241 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]242 <&clk_sandbox 0>,
243 <&clk_sandbox 3>,
244 <&clk_sandbox 2>;
245 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]246 };
247
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200[diff] [blame]248 ccf: clk-ccf {
249 compatible = "sandbox,clk-ccf";
250 };
251
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]252 eth@10002000 {
253 compatible = "sandbox,eth";
254 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]255 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]256 };
257
258 eth_5: eth@10003000 {
259 compatible = "sandbox,eth";
260 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]261 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]262 };
263
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]264 eth_3: sbe5 {
265 compatible = "sandbox,eth";
266 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]267 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]268 };
269
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]270 eth@10004000 {
271 compatible = "sandbox,eth";
272 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]273 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]274 };
275
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]276 firmware {
277 sandbox_firmware: sandbox-firmware {
278 compatible = "sandbox,firmware";
279 };
280 };
281
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]282 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]283 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]284 gpio-controller;
285 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]286 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]287 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]288 };
289
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]290 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]291 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]292 gpio-controller;
293 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]294 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]295 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]296 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]297
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]298 i2c@0 {
299 #address-cells = <1>;
300 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]301 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]302 compatible = "sandbox,i2c";
303 clock-frequency = <100000>;
304 eeprom@2c {
305 reg = <0x2c>;
306 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]307 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]308 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]309
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]310 rtc_0: rtc@43 {
311 reg = <0x43>;
312 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]313 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]314 };
315
316 rtc_1: rtc@61 {
317 reg = <0x61>;
318 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]319 sandbox,emul = <&emul1>;
320 };
321
322 i2c_emul: emul {
323 reg = <0xff>;
324 compatible = "sandbox,i2c-emul-parent";
325 emul_eeprom: emul-eeprom {
326 compatible = "sandbox,i2c-eeprom";
327 sandbox,filename = "i2c.bin";
328 sandbox,size = <256>;
329 };
330 emul0: emul0 {
331 compatible = "sandbox,i2c-rtc";
332 };
333 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]334 compatible = "sandbox,i2c-rtc";
335 };
336 };
337
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]338 sandbox_pmic: sandbox_pmic {
339 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]340 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]341 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]342
343 mc34708: pmic@41 {
344 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]345 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]346 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]347 };
348
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]349 bootcount@0 {
350 compatible = "u-boot,bootcount-rtc";
351 rtc = <&rtc_1>;
352 offset = <0x13>;
353 };
354
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]355 adc@0 {
356 compatible = "sandbox,adc";
357 vdd-supply = <&buck2>;
358 vss-microvolts = <0>;
359 };
360
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]361 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]362 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]363 interrupt-controller;
364 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]365 };
366
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]367 lcd {
368 u-boot,dm-pre-reloc;
369 compatible = "sandbox,lcd-sdl";
370 xres = <1366>;
371 yres = <768>;
372 };
373
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]374 leds {
375 compatible = "gpio-leds";
376
377 iracibble {
378 gpios = <&gpio_a 1 0>;
379 label = "sandbox:red";
380 };
381
382 martinet {
383 gpios = <&gpio_a 2 0>;
384 label = "sandbox:green";
385 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]386
387 default_on {
388 gpios = <&gpio_a 5 0>;
389 label = "sandbox:default_on";
390 default-state = "on";
391 };
392
393 default_off {
394 gpios = <&gpio_a 6 0>;
395 label = "sandbox:default_off";
396 default-state = "off";
397 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]398 };
399
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]400 mbox: mbox {
401 compatible = "sandbox,mbox";
402 #mbox-cells = <1>;
403 };
404
405 mbox-test {
406 compatible = "sandbox,mbox-test";
407 mboxes = <&mbox 100>, <&mbox 1>;
408 mbox-names = "other", "test";
409 };
410
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]411 cpus {
412 cpu-test1 {
413 compatible = "sandbox,cpu_sandbox";
414 u-boot,dm-pre-reloc;
415 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]416
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]417 cpu-test2 {
418 compatible = "sandbox,cpu_sandbox";
419 u-boot,dm-pre-reloc;
420 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]421
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]422 cpu-test3 {
423 compatible = "sandbox,cpu_sandbox";
424 u-boot,dm-pre-reloc;
425 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]426 };
427
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]428 i2s: i2s {
429 compatible = "sandbox,i2s";
430 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700[diff] [blame]431 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]432 };
433
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200[diff] [blame]434 nop-test_0 {
435 compatible = "sandbox,nop_sandbox1";
436 nop-test_1 {
437 compatible = "sandbox,nop_sandbox2";
438 bind = "True";
439 };
440 nop-test_2 {
441 compatible = "sandbox,nop_sandbox2";
442 bind = "False";
443 };
444 };
445
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]446 misc-test {
447 compatible = "sandbox,misc_sandbox";
448 };
449
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]450 mmc2 {
451 compatible = "sandbox,mmc";
452 };
453
454 mmc1 {
455 compatible = "sandbox,mmc";
456 };
457
458 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]459 compatible = "sandbox,mmc";
460 };
461
Simon Glass53a68b32019-02-16 20:24:50 -0700[diff] [blame]462 pch {
463 compatible = "sandbox,pch";
464 };
465
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]466 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]467 compatible = "sandbox,pci";
468 device_type = "pci";
469 #address-cells = <3>;
470 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600[diff] [blame]471 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]472 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]473 pci@0,0 {
474 compatible = "pci-generic";
475 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]476 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]477 };
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]478 pci@1,0 {
479 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]480 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
481 reg = <0x02000814 0 0 0 0
482 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]483 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]484 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]485 p2sb-pci@2,0 {
486 compatible = "sandbox,p2sb";
487 reg = <0x02001010 0 0 0 0>;
488 sandbox,emul = <&p2sb_emul>;
489
490 adder {
491 intel,p2sb-port-id = <3>;
492 compatible = "sandbox,adder";
493 };
494 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]495 pci@1e,0 {
496 compatible = "sandbox,pmc";
497 reg = <0xf000 0 0 0 0>;
498 sandbox,emul = <&pmc_emul1e>;
499 acpi-base = <0x400>;
500 gpe0-dwx-mask = <0xf>;
501 gpe0-dwx-shift-base = <4>;
502 gpe0-dw = <6 7 9>;
503 gpe0-sts = <0x20>;
504 gpe0-en = <0x30>;
505 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]506 pci@1f,0 {
507 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]508 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
509 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]510 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]511 };
512 };
513
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]514 pci-emul0 {
515 compatible = "sandbox,pci-emul-parent";
516 swap_case_emul0_0: emul0@0,0 {
517 compatible = "sandbox,swap-case";
518 };
519 swap_case_emul0_1: emul0@1,0 {
520 compatible = "sandbox,swap-case";
521 use-ea;
522 };
523 swap_case_emul0_1f: emul0@1f,0 {
524 compatible = "sandbox,swap-case";
525 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]526 p2sb_emul: emul@2,0 {
527 compatible = "sandbox,p2sb-emul";
528 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]529 pmc_emul1e: emul@1e,0 {
530 compatible = "sandbox,pmc-emul";
531 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]532 };
533
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]534 pci1: pci-controller1 {
535 compatible = "sandbox,pci";
536 device_type = "pci";
537 #address-cells = <3>;
538 #size-cells = <2>;
539 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
540 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]541 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]542 0x0c 0x00 0x1234 0x5678
543 0x10 0x00 0x1234 0x5678>;
544 pci@10,0 {
545 reg = <0x8000 0 0 0 0>;
546 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]547 };
548
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]549 pci2: pci-controller2 {
550 compatible = "sandbox,pci";
551 device_type = "pci";
552 #address-cells = <3>;
553 #size-cells = <2>;
554 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
555 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
556 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
557 pci@1f,0 {
558 compatible = "pci-generic";
559 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]560 sandbox,emul = <&swap_case_emul2_1f>;
561 };
562 };
563
564 pci-emul2 {
565 compatible = "sandbox,pci-emul-parent";
566 swap_case_emul2_1f: emul2@1f,0 {
567 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]568 };
569 };
570
Ramon Friedc64f19b2019-04-27 11:15:23 +0300[diff] [blame]571 pci_ep: pci_ep {
572 compatible = "sandbox,pci_ep";
573 };
574
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]575 probing {
576 compatible = "simple-bus";
577 test1 {
578 compatible = "denx,u-boot-probe-test";
579 };
580
581 test2 {
582 compatible = "denx,u-boot-probe-test";
583 };
584
585 test3 {
586 compatible = "denx,u-boot-probe-test";
587 };
588
589 test4 {
590 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]591 first-syscon = <&syscon0>;
592 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]593 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]594 };
595 };
596
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]597 pwrdom: power-domain {
598 compatible = "sandbox,power-domain";
599 #power-domain-cells = <1>;
600 };
601
602 power-domain-test {
603 compatible = "sandbox,power-domain-test";
604 power-domains = <&pwrdom 2>;
605 };
606
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]607 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]608 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]609 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]610 };
611
612 pwm2 {
613 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]614 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]615 };
616
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]617 ram {
618 compatible = "sandbox,ram";
619 };
620
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]621 reset@0 {
622 compatible = "sandbox,warm-reset";
623 };
624
625 reset@1 {
626 compatible = "sandbox,reset";
627 };
628
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]629 resetc: reset-ctl {
630 compatible = "sandbox,reset-ctl";
631 #reset-cells = <1>;
632 };
633
634 reset-ctl-test {
635 compatible = "sandbox,reset-ctl-test";
636 resets = <&resetc 100>, <&resetc 2>;
637 reset-names = "other", "test";
638 };
639
Sughosh Ganu23e37512019-12-28 23:58:31 +0530[diff] [blame]640 rng {
641 compatible = "sandbox,sandbox-rng";
642 };
643
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]644 rproc_1: rproc@1 {
645 compatible = "sandbox,test-processor";
646 remoteproc-name = "remoteproc-test-dev1";
647 };
648
649 rproc_2: rproc@2 {
650 compatible = "sandbox,test-processor";
651 internal-memory-mapped;
652 remoteproc-name = "remoteproc-test-dev2";
653 };
654
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]655 panel {
656 compatible = "simple-panel";
657 backlight = <&backlight 0 100>;
658 };
659
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]660 smem@0 {
661 compatible = "sandbox,smem";
662 };
663
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]664 sound {
665 compatible = "sandbox,sound";
666 cpu {
667 sound-dai = <&i2s 0>;
668 };
669
670 codec {
671 sound-dai = <&audio 0>;
672 };
673 };
674
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]675 spi@0 {
676 #address-cells = <1>;
677 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]678 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]679 compatible = "sandbox,spi";
680 cs-gpios = <0>, <&gpio_a 0>;
681 spi.bin@0 {
682 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]683 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]684 spi-max-frequency = <40000000>;
685 sandbox,filename = "spi.bin";
686 };
687 };
688
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]689 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]690 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]691 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]692 };
693
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]694 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]695 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]696 reg = <0x20 5
697 0x28 6
698 0x30 7
699 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]700 };
701
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]702 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]703 compatible = "simple-mfd", "syscon";
704 reg = <0x40 5
705 0x48 6
706 0x50 7
707 0x58 8>;
708 };
709
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]710 timer {
711 compatible = "sandbox,timer";
712 clock-frequency = <1000000>;
713 };
714
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]715 tpm2 {
716 compatible = "sandbox,tpm2";
717 };
718
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]719 uart0: serial {
720 compatible = "sandbox,serial";
721 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]722 };
723
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]724 usb_0: usb@0 {
725 compatible = "sandbox,usb";
726 status = "disabled";
727 hub {
728 compatible = "sandbox,usb-hub";
729 #address-cells = <1>;
730 #size-cells = <0>;
731 flash-stick {
732 reg = <0>;
733 compatible = "sandbox,usb-flash";
734 };
735 };
736 };
737
738 usb_1: usb@1 {
739 compatible = "sandbox,usb";
740 hub {
741 compatible = "usb-hub";
742 usb,device-class = <9>;
743 hub-emul {
744 compatible = "sandbox,usb-hub";
745 #address-cells = <1>;
746 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]747 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]748 reg = <0>;
749 compatible = "sandbox,usb-flash";
750 sandbox,filepath = "testflash.bin";
751 };
752
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]753 flash-stick@1 {
754 reg = <1>;
755 compatible = "sandbox,usb-flash";
756 sandbox,filepath = "testflash1.bin";
757 };
758
759 flash-stick@2 {
760 reg = <2>;
761 compatible = "sandbox,usb-flash";
762 sandbox,filepath = "testflash2.bin";
763 };
764
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]765 keyb@3 {
766 reg = <3>;
767 compatible = "sandbox,usb-keyb";
768 };
769
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]770 };
771 };
772 };
773
774 usb_2: usb@2 {
775 compatible = "sandbox,usb";
776 status = "disabled";
777 };
778
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]779 spmi: spmi@0 {
780 compatible = "sandbox,spmi";
781 #address-cells = <0x1>;
782 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]783 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]784 pm8916@0 {
785 compatible = "qcom,spmi-pmic";
786 reg = <0x0 0x1>;
787 #address-cells = <0x1>;
788 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]789 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]790
791 spmi_gpios: gpios@c000 {
792 compatible = "qcom,pm8916-gpio";
793 reg = <0xc000 0x400>;
794 gpio-controller;
795 gpio-count = <4>;
796 #gpio-cells = <2>;
797 gpio-bank-name="spmi";
798 };
799 };
800 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]801
802 wdt0: wdt@0 {
803 compatible = "sandbox,wdt";
804 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]805
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]806 axi: axi@0 {
807 compatible = "sandbox,axi";
808 #address-cells = <0x1>;
809 #size-cells = <0x1>;
810 store@0 {
811 compatible = "sandbox,sandbox_store";
812 reg = <0x0 0x400>;
813 };
814 };
815
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]816 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]817 #address-cells = <1>;
818 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700[diff] [blame]819 setting = "sunrise ohoka";
820 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700[diff] [blame]821 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]822 chosen-test {
823 compatible = "denx,u-boot-fdt-test";
824 reg = <9 1>;
825 };
826 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]827
828 translation-test@8000 {
829 compatible = "simple-bus";
830 reg = <0x8000 0x4000>;
831
832 #address-cells = <0x2>;
833 #size-cells = <0x1>;
834
835 ranges = <0 0x0 0x8000 0x1000
836 1 0x100 0x9000 0x1000
837 2 0x200 0xA000 0x1000
838 3 0x300 0xB000 0x1000
839 >;
840
Fabien Dessenne22236e02019-05-31 15:11:30 +0200[diff] [blame]841 dma-ranges = <0 0x000 0x10000000 0x1000
842 1 0x100 0x20000000 0x1000
843 >;
844
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]845 dev@0,0 {
846 compatible = "denx,u-boot-fdt-dummy";
847 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]848 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]849 };
850
851 dev@1,100 {
852 compatible = "denx,u-boot-fdt-dummy";
853 reg = <1 0x100 0x1000>;
854
855 };
856
857 dev@2,200 {
858 compatible = "denx,u-boot-fdt-dummy";
859 reg = <2 0x200 0x1000>;
860 };
861
862
863 noxlatebus@3,300 {
864 compatible = "simple-bus";
865 reg = <3 0x300 0x1000>;
866
867 #address-cells = <0x1>;
868 #size-cells = <0x0>;
869
870 dev@42 {
871 compatible = "denx,u-boot-fdt-dummy";
872 reg = <0x42>;
873 };
874 };
875 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]876
877 osd {
878 compatible = "sandbox,sandbox_osd";
879 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]880
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]881 board {
882 compatible = "sandbox,board_sandbox";
883 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]884
885 sandbox_tee {
886 compatible = "sandbox,tee";
887 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]888
889 sandbox_virtio1 {
890 compatible = "sandbox,virtio1";
891 };
892
893 sandbox_virtio2 {
894 compatible = "sandbox,virtio2";
895 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]896
897 pinctrl {
898 compatible = "sandbox,pinctrl";
899 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]900
901 hwspinlock@0 {
902 compatible = "sandbox,hwspinlock";
903 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]904
905 dma: dma {
906 compatible = "sandbox,dma";
907 #dma-cells = <1>;
908
909 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
910 dma-names = "m2m", "tx0", "rx0";
911 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]912
Alex Marginean0649be52019-07-12 10:13:53 +0300[diff] [blame]913 /*
914 * keep mdio-mux ahead of mdio so that the mux is removed first at the
915 * end of the test. If parent mdio is removed first, clean-up of the
916 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
917 * active at the end of the test. That it turn doesn't allow the mdio
918 * class to be destroyed, triggering an error.
919 */
920 mdio-mux-test {
921 compatible = "sandbox,mdio-mux";
922 #address-cells = <1>;
923 #size-cells = <0>;
924 mdio-parent-bus = <&mdio>;
925
926 mdio-ch-test@0 {
927 reg = <0>;
928 };
929 mdio-ch-test@1 {
930 reg = <1>;
931 };
932 };
933
934 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]935 compatible = "sandbox,mdio";
936 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]937};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]938
939#include "sandbox_pmic.dtsi"