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git01.mediatek.com / filogic / uboot / 604e30d9b72728499a669e5f397650670f550cb6 / . / arch / arm / mach-exynos / mmu-arm64.c
blob: 4c154950f73b0d92a90cf1b3b4139b425c38b78d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]2/*
3 * Copyright (C) 2016 Samsung Electronics
4 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]5 */
6
Tom Riniabb9a042024-05-18 20:20:43 -0600[diff] [blame]7#include <common.h>
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]8#include <asm/armv8/mmu.h>
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]9#include <linux/sizes.h>
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]10
Simon Glasse365c842023-02-05 15:39:51 -0700[diff] [blame]11#if IS_ENABLED(CONFIG_EXYNOS7420)
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]12
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]13static struct mm_region exynos7420_mem_map[] = {
14 {
York Sunc7104e52016-06-24 16:46:22 -0700[diff] [blame]15 .virt = 0x10000000UL,
16 .phys = 0x10000000UL,
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]17 .size = 0x10000000UL,
18 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
19 PTE_BLOCK_NON_SHARE |
20 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
21 }, {
York Sunc7104e52016-06-24 16:46:22 -0700[diff] [blame]22 .virt = 0x40000000UL,
23 .phys = 0x40000000UL,
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]24 .size = 0x80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
26 PTE_BLOCK_INNER_SHARE,
27 }, {
28 /* List terminator */
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]29 },
30};
31
32struct mm_region *mem_map = exynos7420_mem_map;
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]33
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]34#elif CONFIG_IS_ENABLED(EXYNOS7870)
35
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]36static struct mm_region exynos7870_mem_map[] = {
37 {
38 .virt = 0x10000000UL,
39 .phys = 0x10000000UL,
40 .size = 0x10000000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
42 PTE_BLOCK_NON_SHARE |
43 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
44 },
45 {
46 .virt = 0x40000000UL,
47 .phys = 0x40000000UL,
48 .size = 0x3E400000UL,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
50 PTE_BLOCK_INNER_SHARE,
51 },
52 {
53 .virt = 0x80000000UL,
54 .phys = 0x80000000UL,
55 .size = 0x40000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
57 PTE_BLOCK_INNER_SHARE,
58 },
59
60 {
61 /* List terminator */
62 },
63};
64
65struct mm_region *mem_map = exynos7870_mem_map;
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]66
67#elif CONFIG_IS_ENABLED(EXYNOS7880)
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]68
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]69static struct mm_region exynos7880_mem_map[] = {
70 {
71 .virt = 0x10000000UL,
72 .phys = 0x10000000UL,
73 .size = 0x10000000UL,
74 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
75 PTE_BLOCK_NON_SHARE |
76 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
77 },
78 {
79 .virt = 0x40000000UL,
80 .phys = 0x40000000UL,
81 .size = 0x3E400000UL,
82 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
83 PTE_BLOCK_INNER_SHARE,
84 },
85 {
86 .virt = 0x80000000UL,
87 .phys = 0x80000000UL,
88 .size = 0x80000000UL,
89 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
90 PTE_BLOCK_INNER_SHARE,
91 },
92
93 {
94 /* List terminator */
95 },
96};
97
98struct mm_region *mem_map = exynos7880_mem_map;
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]99
100#elif IS_ENABLED(CONFIG_EXYNOS850)
101
102static struct mm_region exynos850_mem_map[] = {
103 {
Sam Protsenkoa8152562024-05-25 16:53:30 -0500[diff] [blame]104 /* iRAM */
105 .virt = 0x02000000UL,
106 .phys = 0x02000000UL,
107 .size = SZ_2M,
108 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
109 PTE_BLOCK_NON_SHARE |
110 PTE_BLOCK_PXN | PTE_BLOCK_UXN
111 }, {
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]112 /* Peripheral block */
113 .virt = 0x10000000UL,
114 .phys = 0x10000000UL,
115 .size = SZ_256M,
116 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
117 PTE_BLOCK_NON_SHARE |
118 PTE_BLOCK_PXN | PTE_BLOCK_UXN
119 }, {
120 /* DDR, 32-bit area */
121 .virt = 0x80000000UL,
122 .phys = 0x80000000UL,
123 .size = SZ_2G,
124 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
125 PTE_BLOCK_INNER_SHARE
126 }, {
127 /* DDR, 64-bit area */
128 .virt = 0x880000000UL,
129 .phys = 0x880000000UL,
130 .size = SZ_2G,
131 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
132 PTE_BLOCK_INNER_SHARE
133 }, {
134 /* List terminator */
135 }
136};
137
138struct mm_region *mem_map = exynos850_mem_map;
139
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]140#endif