blob: 9aee3ff786cba830eda534cdec6933eaa71e31d2 [file] [log] [blame]
Chris Zhang52d17612010-01-06 13:34:05 -08001/*
2 * (C) Copyright 2010, Chris Zhang <chris@seamicro.com>
3 *
4 * Author: Chris Zhang <chris@seamicro.com>
5 * This code is based on ehci freescale driver
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Chris Zhang52d17612010-01-06 13:34:05 -08008 */
9#include <common.h>
10#include <usb.h>
11
12#include "ehci.h"
Chris Zhang52d17612010-01-06 13:34:05 -080013
14/*
15 * Create the appropriate control structures to manage
16 * a new EHCI host controller.
17 */
Troy Kisky7d6bbb92013-10-10 15:27:57 -070018int ehci_hcd_init(int index, enum usb_init_type init,
19 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Chris Zhang52d17612010-01-06 13:34:05 -080020{
Lucas Stach3494a4c2012-09-26 00:14:35 +020021 *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
22 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
23 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Chris Zhang52d17612010-01-06 13:34:05 -080024 return 0;
25}
26
27/*
28 * Destroy the appropriate control structures corresponding
29 * the the EHCI host controller.
30 */
Lucas Stach3494a4c2012-09-26 00:14:35 +020031int ehci_hcd_stop(int index)
Chris Zhang52d17612010-01-06 13:34:05 -080032{
33 return 0;
34}