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git01.mediatek.com / filogic / uboot / 5ff1e249fa72fbc165e1ad8bdbd4e093c4bc6d95 / . / board / sunxi / gmac.c
blob: 1fa54ed72de9a7389ec5dfce97b97bf478a4fb5e [file] [log] [blame]
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]1#include <common.h>
2#include <netdev.h>
3#include <miiphy.h>
4#include <asm/gpio.h>
5#include <asm/io.h>
6#include <asm/arch/clock.h>
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]7
Hans de Goede42cbbe32016-03-17 13:53:03 +0100[diff] [blame]8void eth_init_board(void)
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]9{
10 int pin;
11 struct sunxi_ccm_reg *const ccm =
12 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
13
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]14 /* Set MII clock */
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]15#ifdef CONFIG_RGMII
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]16 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
17 CCM_GMAC_CTRL_GPIT_RGMII);
Hans de Goedebf880fe2015-01-25 12:10:48 +0100[diff] [blame]18 setbits_le32(&ccm->gmac_clk_cfg,
19 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]20#else
21 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
22 CCM_GMAC_CTRL_GPIT_MII);
23#endif
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]24
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]25#ifndef CONFIG_MACH_SUN6I
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]26 /* Configure pin mux settings for GMAC */
Stefan Mavrodieveaee8582017-11-03 08:56:51 +0200[diff] [blame]27#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
28 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
29#else
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]30 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
Stefan Mavrodieveaee8582017-11-03 08:56:51 +0200[diff] [blame]31#endif
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]32#ifdef CONFIG_RGMII
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]33 /* skip unused pins in RGMII mode */
34 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
35 continue;
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]36#endif
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]37 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]38 sunxi_gpio_set_drv(pin, 3);
39 }
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]40#elif defined CONFIG_RGMII
41 /* Configure sun6i RGMII mode pin mux settings */
42 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]43 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]44 sunxi_gpio_set_drv(pin, 3);
45 }
46 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]47 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]48 sunxi_gpio_set_drv(pin, 3);
49 }
50 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]51 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]52 sunxi_gpio_set_drv(pin, 3);
53 }
54 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]55 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]56 sunxi_gpio_set_drv(pin, 3);
57 }
58#elif defined CONFIG_GMII
59 /* Configure sun6i GMII mode pin mux settings */
60 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]61 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]62 sunxi_gpio_set_drv(pin, 2);
63 }
64#else
65 /* Configure sun6i MII mode pin mux settings */
66 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]67 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]68 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]69 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]70 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]71 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]72 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]73 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]74 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]75 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]76#endif
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]77}