blob: d21e5042a67a77e71d4113fc34a8ab07207d271b [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&gic>;
9
10 /* external reference clock */
11 clk_refclk: clk-refclk {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <25000000>;
15 clock-output-names = "refclk";
16 };
17
18 ahb {
19 rstc: reset-controller@f0801000 {
20 compatible = "nuvoton,npcm845-reset", "syscon",
21 "simple-mfd";
22 reg = <0x0 0xf0801000 0x0 0xC4>;
23 rstc1: reset-controller1 {
24 compatible = "syscon-reset";
25 #reset-cells = <1>;
26 regmap = <&rstc>;
27 offset = <NPCM8XX_RESET_IPSRST1>;
28 mask = <0xFFFFFFFF>;
29 };
30 rstc2: reset-controller2 {
31 compatible = "syscon-reset";
32 #reset-cells = <1>;
33 regmap = <&rstc>;
34 offset = <NPCM8XX_RESET_IPSRST2>;
35 mask = <0xFFFFFFFF>;
36 };
37 rstc3: reset-controller3 {
38 compatible = "syscon-reset";
39 #reset-cells = <1>;
40 regmap = <&rstc>;
41 offset = <NPCM8XX_RESET_IPSRST3>;
42 mask = <0xFFFFFFFF>;
43 };
44 rstc4: reset-controller4 {
45 compatible = "syscon-reset";
46 #reset-cells = <1>;
47 regmap = <&rstc>;
48 offset = <NPCM8XX_RESET_IPSRST4>;
49 mask = <0xFFFFFFFF>;
50 };
51 };
52
53 clk: clock-controller@f0801000 {
54 compatible = "nuvoton,npcm845-clk", "syscon";
55 #clock-cells = <1>;
56 clock-controller;
57 reg = <0x0 0xf0801000 0x0 0x1000>;
58 clock-names = "refclk";
59 clocks = <&clk_refclk>;
60 };
61
Jim Liu89b26542022-11-28 10:32:44 +080062 ehci1: usb@f0828100 {
63 compatible = "nuvoton,npcm845-ehci";
64 reg = <0x0 0xf0828100 0x0 0x1000>;
65 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
66 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
67 status = "disabled";
68 };
69
70 ehci2: usb@f082a100 {
71 compatible = "nuvoton,npcm845-ehci";
72 reg = <0x0 0xf082a100 0x0 0x1000>;
73 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
74 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
75 status = "disabled";
76 };
77
78 ohci1: usb@f0829000 {
79 compatible = "nuvoton,npcm845-ohci";
80 reg = <0x0 0xF0829000 0x0 0x1000>;
81 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
82 status = "disabled";
83 };
84
85 ohci2: usb@f082b000 {
86 compatible = "nuvoton,npcm845-ohci";
87 reg = <0x0 0xF082B000 0x0 0x1000>;
88 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
89 status = "disabled";
90 };
91
92 usbphy {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <0>;
96 syscon = <&gcr>;
97 usbphy1: usbphy@1 {
98 compatible = "nuvoton,npcm845-usb-phy";
99 #phy-cells = <1>;
100 reg = <1>;
101 resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
102 status = "disabled";
103 };
104 usbphy2: usbphy@2 {
105 compatible = "nuvoton,npcm845-usb-phy";
106 #phy-cells = <1>;
107 reg = <2>;
108 resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
109 status = "disabled";
110 };
111 usbphy3: usbphy@3 {
112 compatible = "nuvoton,npcm845-usb-phy";
113 #phy-cells = <1>;
114 reg = <3>;
115 resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
116 status = "disabled";
117 };
118 };
119
120 udc0:udc@f0830100 {
121 compatible = "nuvoton,npcm845-udc";
122 reg = <0x0 0xf0830100 0x0 0x100
123 0x0 0xfffb0000 0x0 0x800>;
124 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&clk NPCM8XX_CLK_SU>;
126 clock-names = "clk_usb_bridge";
127 resets = <&rstc3 NPCM8XX_RESET_UDC0>;
128 status = "disable";
129 };
130
131 udc1:udc@f0831100 {
132 compatible = "nuvoton,npcm845-udc";
133 reg = <0x0 0xf0831100 0x0 0x100
134 0x0 0xfffb0800 0x0 0x800>;
135 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clk NPCM8XX_CLK_SU>;
137 clock-names = "clk_usb_bridge";
138 resets = <&rstc1 NPCM8XX_RESET_UDC1>;
139 status = "disable";
140 };
141
142 udc2:udc@f0832100 {
143 compatible = "nuvoton,npcm845-udc";
144 reg = <0x0 0xf0832100 0x0 0x100
145 0x0 0xfffb1000 0x0 0x800>;
146 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clk NPCM8XX_CLK_SU>;
148 clock-names = "clk_usb_bridge";
149 resets = <&rstc1 NPCM8XX_RESET_UDC2>;
150 status = "disable";
151 };
152
153 udc3:udc@f0833100 {
154 compatible = "nuvoton,npcm845-udc";
155 reg = <0x0 0xf0833100 0x0 0x100
156 0x0 0xfffb1800 0x0 0x800>;
157 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clk NPCM8XX_CLK_SU>;
159 clock-names = "clk_usb_bridge";
160 resets = <&rstc1 NPCM8XX_RESET_UDC3>;
161 status = "disable";
162 };
163
164 udc4:udc@f0834100 {
165 compatible = "nuvoton,npcm845-udc";
166 reg = <0x0 0xf0834100 0x0 0x100
167 0x0 0xfffb2000 0x0 0x800>;
168 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&clk NPCM8XX_CLK_SU>;
170 clock-names = "clk_usb_bridge";
171 resets = <&rstc1 NPCM8XX_RESET_UDC4>;
172 status = "disable";
173 };
174
175 udc5:udc@f0835100 {
176 compatible = "nuvoton,npcm845-udc";
177 reg = <0x0 0xf0835100 0x0 0x100
178 0x0 0xfffb2800 0x0 0x800>;
179 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clk NPCM8XX_CLK_SU>;
181 clock-names = "clk_usb_bridge";
182 resets = <&rstc1 NPCM8XX_RESET_UDC5>;
183 status = "disable";
184 };
185
186 udc6:udc@f0836100 {
187 compatible = "nuvoton,npcm845-udc";
188 reg = <0x0 0xf0836100 0x0 0x100
189 0x0 0xfffb3000 0x0 0x800>;
190 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clk NPCM8XX_CLK_SU>;
192 clock-names = "clk_usb_bridge";
193 resets = <&rstc1 NPCM8XX_RESET_UDC6>;
194 status = "disable";
195 };
196
197 udc7:udc@f0837100 {
198 compatible = "nuvoton,npcm845-udc";
199 reg = <0x0 0xf0837100 0x0 0x100
200 0x0 0xfffb3800 0x0 0x800>;
201 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clk NPCM8XX_CLK_SU>;
203 clock-names = "clk_usb_bridge";
204 resets = <&rstc3 NPCM8XX_RESET_UDC7>;
205 status = "disable";
206 };
207
208 udc8:udc@f0838100 {
209 compatible = "nuvoton,npcm845-udc";
210 reg = <0x0 0xf0838100 0x0 0x100
211 0x0 0xfffb4000 0x0 0x800>;
212 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clk NPCM8XX_CLK_SU>;
214 clock-names = "clk_usb_bridge";
215 resets = <&rstc3 NPCM8XX_RESET_UDC8>;
216 status = "disable";
217 };
218
219 udc9:udc@f0839100 {
220 compatible = "nuvoton,npcm845-udc";
221 reg = <0x0 0xf0839100 0x0 0x100
222 0x0 0xfffb4800 0x0 0x800>;
223 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clk NPCM8XX_CLK_SU>;
225 clock-names = "clk_usb_bridge";
226 resets = <&rstc3 NPCM8XX_RESET_UDC9>;
227 status = "disable";
228 };
229
Jim Liu147c0002022-09-27 16:45:15 +0800230 apb {
231 serial0: serial@0 {
232 compatible = "nuvoton,npcm845-uart";
233 reg = <0x0 0x1000>;
234 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
235 clock-frequency = <24000000>;
236 status = "disabled";
237 };
238
239 gpio0: gpio0@10000 {
Jim Liu89b26542022-11-28 10:32:44 +0800240 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800241 reg = <0x10000 0xB0>;
242 #gpio-cells = <2>;
243 gpio-controller;
244 gpio-bank-name = "gpio0";
245 };
246
247 gpio1: gpio1@11000 {
Jim Liu89b26542022-11-28 10:32:44 +0800248 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800249 reg = <0x11000 0xB0>;
250 #gpio-cells = <2>;
251 gpio-controller;
252 gpio-bank-name = "gpio1";
253 };
254
255 gpio2: gpio2@12000 {
Jim Liu89b26542022-11-28 10:32:44 +0800256 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800257 reg = <0x12000 0xB0>;
258 #gpio-cells = <2>;
259 gpio-controller;
260 gpio-bank-name = "gpio2";
261 };
262
263 gpio3: gpio3@13000 {
Jim Liu89b26542022-11-28 10:32:44 +0800264 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800265 reg = <0x13000 0xB0>;
266 #gpio-cells = <2>;
267 gpio-controller;
268 gpio-bank-name = "gpio3";
269 };
270
271 gpio4: gpio4@14000 {
Jim Liu89b26542022-11-28 10:32:44 +0800272 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800273 reg = <0x14000 0xB0>;
274 #gpio-cells = <2>;
275 gpio-controller;
276 gpio-bank-name = "gpio4";
277 };
278
279 gpio5: gpio5@15000 {
Jim Liu89b26542022-11-28 10:32:44 +0800280 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800281 reg = <0x15000 0xB0>;
282 #gpio-cells = <2>;
283 gpio-controller;
284 gpio-bank-name = "gpio5";
285 };
286
287 gpio6: gpio6@16000 {
Jim Liu89b26542022-11-28 10:32:44 +0800288 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800289 reg = <0x16000 0xB0>;
290 #gpio-cells = <2>;
291 gpio-controller;
292 gpio-bank-name = "gpio6";
293 };
294
295 gpio7: gpio7@17000 {
Jim Liu89b26542022-11-28 10:32:44 +0800296 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800297 reg = <0x17000 0xB0>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 gpio-bank-name = "gpio7";
301 };
302 };
303 };
Jim Liu89b26542022-11-28 10:32:44 +0800304 pinctrl: pinctrl@f0800000 {
305 compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
306 reg = <0x0 0xf0010000 0x0 0x8000>;
307 syscon-gcr = <&gcr>;
308 syscon-rst = <&rstc>;
309 status = "okay";
310
311 iox1_pins: iox1-pins {
312 groups = "iox1";
313 function = "iox1";
314 };
315 iox2_pins: iox2-pins {
316 groups = "iox2";
317 function = "iox2";
318 };
319 smb1d_pins: smb1d-pins {
320 groups = "smb1d";
321 function = "smb1d";
322 };
323 smb2d_pins: smb2d-pins {
324 groups = "smb2d";
325 function = "smb2d";
326 };
327 lkgpo1_pins: lkgpo1-pins {
328 groups = "lkgpo1";
329 function = "lkgpo1";
330 };
331 lkgpo2_pins: lkgpo2-pins {
332 groups = "lkgpo2";
333 function = "lkgpo2";
334 };
335 ioxh_pins: ioxh-pins {
336 groups = "ioxh";
337 function = "ioxh";
338 };
339 gspi_pins: gspi-pins {
340 groups = "gspi";
341 function = "gspi";
342 };
343 smb5b_pins: smb5b-pins {
344 groups = "smb5b";
345 function = "smb5b";
346 };
347 smb5c_pins: smb5c-pins {
348 groups = "smb5c";
349 function = "smb5c";
350 };
351 lkgpo0_pins: lkgpo0-pins {
352 groups = "lkgpo0";
353 function = "lkgpo0";
354 };
355 pspi_pins: pspi-pins {
356 groups = "pspi";
357 function = "pspi";
358 };
359 vgadig_pins: vgadig-pins {
360 groups = "vgadig";
361 function = "vgadig";
362 };
363 jm1_pins: jm1-pins {
364 groups = "jm1";
365 function = "jm1";
366 };
367 jm2_pins: jm2-pins {
368 groups = "jm2";
369 function = "jm2";
370 };
371 smb4b_pins: smb4b-pins {
372 groups = "smb4b";
373 function = "smb4b";
374 };
375 smb4c_pins: smb4c-pins {
376 groups = "smb4c";
377 function = "smb4c";
378 };
379 smb15_pins: smb15-pins {
380 groups = "smb15";
381 function = "smb15";
382 };
383 smb16_pins: smb16-pins {
384 groups = "smb16";
385 function = "smb16";
386 };
387 smb17_pins: smb17-pins {
388 groups = "smb17";
389 function = "smb17";
390 };
391 smb18_pins: smb18-pins {
392 groups = "smb18";
393 function = "smb18";
394 };
395 smb19_pins: smb19-pins {
396 groups = "smb19";
397 function = "smb19";
398 };
399 smb20_pins: smb20-pins {
400 groups = "smb20";
401 function = "smb20";
402 };
403 smb21_pins: smb21-pins {
404 groups = "smb21";
405 function = "smb21";
406 };
407 smb22_pins: smb22-pins {
408 groups = "smb22";
409 function = "smb22";
410 };
411 smb23_pins: smb23-pins {
412 groups = "smb23";
413 function = "smb23";
414 };
415 smb4d_pins: smb4d-pins {
416 groups = "smb4d";
417 function = "smb4d";
418 };
419 smb14_pins: smb14-pins {
420 groups = "smb14";
421 function = "smb14";
422 };
423 smb5_pins: smb5-pins {
424 groups = "smb5";
425 function = "smb5";
426 };
427 smb4_pins: smb4-pins {
428 groups = "smb4";
429 function = "smb4";
430 };
431 smb3_pins: smb3-pins {
432 groups = "smb3";
433 function = "smb3";
434 };
435 spi0cs1_pins: spi0cs1-pins {
436 groups = "spi0cs1";
437 function = "spi0cs1";
438 };
439 spi0cs2_pins: spi0cs2-pins {
440 groups = "spi0cs2";
441 function = "spi0cs2";
442 };
443 spi0cs3_pins: spi0cs3-pins {
444 groups = "spi0cs3";
445 function = "spi0cs3";
446 };
447 smb3c_pins: smb3c-pins {
448 groups = "smb3c";
449 function = "smb3c";
450 };
451 smb3b_pins: smb3b-pins {
452 groups = "smb3b";
453 function = "smb3b";
454 };
455 hsi1a_pins: hsi1a-pins {
456 groups = "hsi1a";
457 function = "hsi1a";
458 };
459 hsi1b_pins: hsi1b-pins {
460 groups = "hsi1b";
461 function = "hsi1b";
462 };
463 hsi1c_pins: hsi1c-pins {
464 groups = "hsi1c";
465 function = "hsi1c";
466 };
467 hsi2a_pins: hsi2a-pins {
468 groups = "hsi2a";
469 function = "hsi2a";
470 };
471 hsi2b_pins: hsi2b-pins {
472 groups = "hsi2b";
473 function = "hsi2b";
474 };
475 hsi2c_pins: hsi2c-pins {
476 groups = "hsi2c";
477 function = "hsi2c";
478 };
479 bmcuart0a_pins: bmcuart0a-pins {
480 groups = "bmcuart0a";
481 function = "bmcuart0a";
482 };
483 bmcuart0b_pins: bmcuart0b-pins {
484 groups = "bmcuart0b";
485 function = "bmcuart0b";
486 };
487 bmcuart1_pins: bmcuart1-pins {
488 groups = "bmcuart1";
489 function = "bmcuart1";
490 };
491 bu4_pins: bu4-pins {
492 groups = "bu4";
493 function = "bu4";
494 };
495 bu5_pins: bu5-pins {
496 groups = "bu5";
497 function = "bu5";
498 };
499 bu6_pins: bu6-pins {
500 groups = "bu6";
501 function = "bu6";
502 };
503 r1err_pins: r1err-pins {
504 groups = "r1err";
505 function = "r1err";
506 };
507 r1md_pins: r1md-pins {
508 groups = "r1md";
509 function = "r1md";
510 };
511 r1oen_pins: r1oen-pins {
512 groups = "r1oen";
513 function = "r1oen";
514 };
515 r1en_pins: r1en-pins {
516 groups = "r1en";
517 function = "r1en";
518 };
519 r2oen_pins: r2oen-pins {
520 groups = "r2oen";
521 function = "r2oen";
522 };
523 r2en_pins: r2en-pins {
524 groups = "r2en";
525 function = "r2en";
526 };
527 rmii3_pins: rmii3_pins {
528 groups = "rmii3";
529 function = "rmii3";
530 };
531 r3oen_pins: r3oen-pins {
532 groups = "r3oen";
533 function = "r3oen";
534 };
535 r3en_pins: r3en-pins {
536 groups = "r3en";
537 function = "r3en";
538 };
539 smb3d_pins: smb3d-pins {
540 groups = "smb3d";
541 function = "smb3d";
542 };
543 fanin0_pins: fanin0-pins {
544 groups = "fanin0";
545 function = "fanin0";
546 };
547 fanin1_pins: fanin1-pins {
548 groups = "fanin1";
549 function = "fanin1";
550 };
551 fanin2_pins: fanin2-pins {
552 groups = "fanin2";
553 function = "fanin2";
554 };
555 fanin3_pins: fanin3-pins {
556 groups = "fanin3";
557 function = "fanin3";
558 };
559 fanin4_pins: fanin4-pins {
560 groups = "fanin4";
561 function = "fanin4";
562 };
563 fanin5_pins: fanin5-pins {
564 groups = "fanin5";
565 function = "fanin5";
566 };
567 fanin6_pins: fanin6-pins {
568 groups = "fanin6";
569 function = "fanin6";
570 };
571 fanin7_pins: fanin7-pins {
572 groups = "fanin7";
573 function = "fanin7";
574 };
575 fanin8_pins: fanin8-pins {
576 groups = "fanin8";
577 function = "fanin8";
578 };
579 fanin9_pins: fanin9-pins {
580 groups = "fanin9";
581 function = "fanin9";
582 };
583 fanin10_pins: fanin10-pins {
584 groups = "fanin10";
585 function = "fanin10";
586 };
587 fanin11_pins: fanin11-pins {
588 groups = "fanin11";
589 function = "fanin11";
590 };
591 fanin12_pins: fanin12-pins {
592 groups = "fanin12";
593 function = "fanin12";
594 };
595 fanin13_pins: fanin13-pins {
596 groups = "fanin13";
597 function = "fanin13";
598 };
599 fanin14_pins: fanin14-pins {
600 groups = "fanin14";
601 function = "fanin14";
602 };
603 fanin15_pins: fanin15-pins {
604 groups = "fanin15";
605 function = "fanin15";
606 };
607 pwm0_pins: pwm0-pins {
608 groups = "pwm0";
609 function = "pwm0";
610 };
611 pwm1_pins: pwm1-pins {
612 groups = "pwm1";
613 function = "pwm1";
614 };
615 pwm2_pins: pwm2-pins {
616 groups = "pwm2";
617 function = "pwm2";
618 };
619 pwm3_pins: pwm3-pins {
620 groups = "pwm3";
621 function = "pwm3";
622 };
623 r2_pins: r2-pins {
624 groups = "r2";
625 function = "r2";
626 };
627 r2err_pins: r2err-pins {
628 groups = "r2err";
629 function = "r2err";
630 };
631 r2md_pins: r2md-pins {
632 groups = "r2md";
633 function = "r2md";
634 };
635 r3rxer_pins: r3rxer_pins {
636 groups = "r3rxer";
637 function = "r3rxer";
638 };
639 ga20kbc_pins: ga20kbc-pins {
640 groups = "ga20kbc";
641 function = "ga20kbc";
642 };
643 smb5d_pins: smb5d-pins {
644 groups = "smb5d";
645 function = "smb5d";
646 };
647 lpc_pins: lpc-pins {
648 groups = "lpc";
649 function = "lpc";
650 };
651 espi_pins: espi-pins {
652 groups = "espi";
653 function = "espi";
654 };
655 rg1_pins: rg1-pins {
656 groups = "rg1";
657 function = "rg1";
658 };
659 rg1mdio_pins: rg1mdio-pins {
660 groups = "rg1mdio";
661 function = "rg1mdio";
662 };
663 rg2_pins: rg2-pins {
664 groups = "rg2";
665 function = "rg2";
666 };
667 ddr_pins: ddr-pins {
668 groups = "ddr";
669 function = "ddr";
670 };
671 i3c0_pins: i3c0-pins {
672 groups = "i3c0";
673 function = "i3c0";
674 };
675 i3c1_pins: i3c1-pins {
676 groups = "i3c1";
677 function = "i3c1";
678 };
679 i3c2_pins: i3c2-pins {
680 groups = "i3c2";
681 function = "i3c2";
682 };
683 i3c3_pins: i3c3-pins {
684 groups = "i3c3";
685 function = "i3c3";
686 };
687 i3c4_pins: i3c4-pins {
688 groups = "i3c4";
689 function = "i3c4";
690 };
691 i3c5_pins: i3c5-pins {
692 groups = "i3c5";
693 function = "i3c5";
694 };
695 smb0_pins: smb0-pins {
696 groups = "smb0";
697 function = "smb0";
698 };
699 smb1_pins: smb1-pins {
700 groups = "smb1";
701 function = "smb1";
702 };
703 smb2_pins: smb2-pins {
704 groups = "smb2";
705 function = "smb2";
706 };
707 smb2c_pins: smb2c-pins {
708 groups = "smb2c";
709 function = "smb2c";
710 };
711 smb2b_pins: smb2b-pins {
712 groups = "smb2b";
713 function = "smb2b";
714 };
715 smb1c_pins: smb1c-pins {
716 groups = "smb1c";
717 function = "smb1c";
718 };
719 smb1b_pins: smb1b-pins {
720 groups = "smb1b";
721 function = "smb1b";
722 };
723 smb8_pins: smb8-pins {
724 groups = "smb8";
725 function = "smb8";
726 };
727 smb9_pins: smb9-pins {
728 groups = "smb9";
729 function = "smb9";
730 };
731 smb10_pins: smb10-pins {
732 groups = "smb10";
733 function = "smb10";
734 };
735 smb11_pins: smb11-pins {
736 groups = "smb11";
737 function = "smb11";
738 };
739 sd1_pins: sd1-pins {
740 groups = "sd1";
741 function = "sd1";
742 };
743 sd1pwr_pins: sd1pwr-pins {
744 groups = "sd1pwr";
745 function = "sd1pwr";
746 };
747 pwm4_pins: pwm4-pins {
748 groups = "pwm4";
749 function = "pwm4";
750 };
751 pwm5_pins: pwm5-pins {
752 groups = "pwm5";
753 function = "pwm5";
754 };
755 pwm6_pins: pwm6-pins {
756 groups = "pwm6";
757 function = "pwm6";
758 };
759 pwm7_pins: pwm7-pins {
760 groups = "pwm7";
761 function = "pwm7";
762 };
763 pwm8_pins: pwm8-pins {
764 groups = "pwm8";
765 function = "pwm8";
766 };
767 pwm9_pins: pwm9-pins {
768 groups = "pwm9";
769 function = "pwm9";
770 };
771 pwm10_pins: pwm10-pins {
772 groups = "pwm10";
773 function = "pwm10";
774 };
775 pwm11_pins: pwm11-pins {
776 groups = "pwm11";
777 function = "pwm11";
778 };
779 mmc8_pins: mmc8-pins {
780 groups = "mmc8";
781 function = "mmc8";
782 };
783 mmc_pins: mmc-pins {
784 groups = "mmc";
785 function = "mmc";
786 };
787 mmcwp_pins: mmcwp-pins {
788 groups = "mmcwp";
789 function = "mmcwp";
790 };
791 mmccd_pins: mmccd-pins {
792 groups = "mmccd";
793 function = "mmccd";
794 };
795 mmcrst_pins: mmcrst-pins {
796 groups = "mmcrst";
797 function = "mmcrst";
798 };
799 clkout_pins: clkout-pins {
800 groups = "clkout";
801 function = "clkout";
802 };
803 serirq_pins: serirq-pins {
804 groups = "serirq";
805 function = "serirq";
806 };
807 scipme_pins: scipme-pins {
808 groups = "scipme";
809 function = "scipme";
810 };
811 sci_pins: sci-pins {
812 groups = "sci";
813 function = "sci";
814 };
815 smb6_pins: smb6-pins {
816 groups = "smb6";
817 function = "smb6";
818 };
819 smb7_pins: smb7-pins {
820 groups = "smb7";
821 function = "smb7";
822 };
823 spi1_pins: spi1-pins {
824 groups = "spi1";
825 function = "spi1";
826 };
827 spi1d23_pins: spi1d23-pins {
828 groups = "spi1d23";
829 function = "spi1d23";
830 };
831 faninx_pins: faninx-pins {
832 groups = "faninx";
833 function = "faninx";
834 };
835 r1_pins: r1-pins {
836 groups = "r1";
837 function = "r1";
838 };
839 spi3_pins: spi3-pins {
840 groups = "spi3";
841 function = "spi3";
842 };
843 spi3cs1_pins: spi3cs1-pins {
844 groups = "spi3cs1";
845 function = "spi3cs1";
846 };
847 spi3quad_pins: spi3quad-pins {
848 groups = "spi3quad";
849 function = "spi3quad";
850 };
851 spi3cs2_pins: spi3cs2-pins {
852 groups = "spi3cs2";
853 function = "spi3cs2";
854 };
855 spi3cs3_pins: spi3cs3-pins {
856 groups = "spi3cs3";
857 function = "spi3cs3";
858 };
859 nprd_smi_pins: nprd-smi-pins {
860 groups = "nprd_smi";
861 function = "nprd_smi";
862 };
863 smb0b_pins: smb0b-pins {
864 groups = "smb0b";
865 function = "smb0b";
866 };
867 smb0c_pins: smb0c-pins {
868 groups = "smb0c";
869 function = "smb0c";
870 };
871 smb0den_pins: smb0den-pins {
872 groups = "smb0den";
873 function = "smb0den";
874 };
875 smb0d_pins: smb0d-pins {
876 groups = "smb0d";
877 function = "smb0d";
878 };
879 rg2mdio_pins: rg2mdio-pins {
880 groups = "rg2mdio";
881 function = "rg2mdio";
882 };
883 rg2refck_pins: rg2refck-pins {
884 groups = "rg2refck";
885 function = "rg2refck";
886 };
887 wdog1_pins: wdog1-pins {
888 groups = "wdog1";
889 function = "wdog1";
890 };
891 wdog2_pins: wdog2-pins {
892 groups = "wdog2";
893 function = "wdog2";
894 };
895 smb12_pins: smb12-pins {
896 groups = "smb12";
897 function = "smb12";
898 };
899 smb13_pins: smb13-pins {
900 groups = "smb13";
901 function = "smb13";
902 };
903 spix_pins: spix-pins {
904 groups = "spix";
905 function = "spix";
906 };
907 spixcs1_pins: spixcs1-pins {
908 groups = "spixcs1";
909 function = "spixcs1";
910 };
911 clkreq_pins: clkreq-pins {
912 groups = "clkreq";
913 function = "clkreq";
914 };
915 hgpio0_pins: hgpio0-pins {
916 groups = "hgpio0";
917 function = "hgpio0";
918 };
919 hgpio1_pins: hgpio1-pins {
920 groups = "hgpio1";
921 function = "hgpio1";
922 };
923 hgpio2_pins: hgpio2-pins {
924 groups = "hgpio2";
925 function = "hgpio2";
926 };
927 hgpio3_pins: hgpio3-pins {
928 groups = "hgpio3";
929 function = "hgpio3";
930 };
931 hgpio4_pins: hgpio4-pins {
932 groups = "hgpio4";
933 function = "hgpio4";
934 };
935 hgpio5_pins: hgpio5-pins {
936 groups = "hgpio5";
937 function = "hgpio5";
938 };
939 hgpio6_pins: hgpio6-pins {
940 groups = "hgpio6";
941 function = "hgpio6";
942 };
943 hgpio7_pins: hgpio7-pins {
944 groups = "hgpio7";
945 function = "hgpio7";
946 };
947 jtag2_pins: jtag2-pins {
948 groups = "jtag2";
949 function = "jtag2";
950 };
951 };
Jim Liu147c0002022-09-27 16:45:15 +0800952};