blob: 5ba9f862e14a3a65c8700725308b0ff58271b2f2 [file] [log] [blame]
Alexey Brodkin4b2705b2018-05-28 15:27:43 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 */
5
6#include <common.h>
7#include <dwmmc.h>
8#include <malloc.h>
9
Alexey Brodkind4472c82018-11-27 09:46:59 +030010#include <asm/arcregs.h>
11
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030012DECLARE_GLOBAL_DATA_PTR;
13
Alexey Brodkind4472c82018-11-27 09:46:59 +030014#define ARC_PERIPHERAL_BASE 0xF0000000
15
16#define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
17#define CGU_ARC_FMEAS_ARC_START BIT(31)
18#define CGU_ARC_FMEAS_ARC_DONE BIT(30)
19#define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
20#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
21#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
22
23#define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
24
25int mach_cpu_init(void)
26{
27 int rcnt, fcnt;
28 u32 data;
29
30 /* Start frequency measurement */
31 writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
32
33 /* Poll DONE bit */
34 do {
35 data = readl(CGU_ARC_FMEAS_ARC);
36 } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
37
38 /* Amount of reference 100 MHz clocks */
39 rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
40 CGU_ARC_FMEAS_ARC_CNT_MASK);
41
42 /* Amount of CPU clocks */
43 fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
44 CGU_ARC_FMEAS_ARC_CNT_MASK);
45
46 gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
47
48 return 0;
49}
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030050
Alexey Brodkinb347f752019-07-18 15:51:25 +030051int board_early_init_r(void)
52{
53#define EMSDP_PSRAM_BASE 0xf2001000
54#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
55#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
56#define CRE_ENABLE BIT(31)
57#define CRE_DRIVE_CMD BIT(6)
58
59#define PSRAM_RCR_DPD BIT(1)
60#define PSRAM_RCR_PAGE_MODE BIT(7)
61
62/*
63 * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
64 * thus "<< 1".
65 */
66#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
67
68 // Switch PSRAM controller to command mode
69 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
70 // Program Refresh Configuration Register (RCR) for BANK0
71 writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
72 // Switch PSRAM controller back to memory mode
73 writel(0, PSRAM_FLASH_CONFIG_REG_0);
74
75
76 // Switch PSRAM controller to command mode
77 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
78 // Program Refresh Configuration Register (RCR) for BANK1
79 writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
80 // Switch PSRAM controller back to memory mode
81 writel(0, PSRAM_FLASH_CONFIG_REG_1);
82
83 printf("PSRAM initialized.\n");
84
85 return 0;
86}
87
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030088#define CREG_BASE 0xF0001000
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +030089#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
90#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
Alexey Brodkindbf9fa22018-11-27 09:47:01 +030091#define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030092
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +030093/* Bits in CREG_BOOT register */
94#define CREG_BOOT_WP_BIT BIT(8)
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030095
96void reset_cpu(ulong addr)
97{
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +030098 writel(1, CREG_IP_SW_RESET);
Alexey Brodkin4b2705b2018-05-28 15:27:43 +030099 while (1)
100 ; /* loop forever till reset */
101}
102
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300103static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300104{
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +0300105 u32 creg_boot = readl(CREG_BOOT);
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300106
107 if (!strcmp(argv[1], "unlock"))
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +0300108 creg_boot &= ~CREG_BOOT_WP_BIT;
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300109 else if (!strcmp(argv[1], "lock"))
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +0300110 creg_boot |= CREG_BOOT_WP_BIT;
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300111 else
112 return CMD_RET_USAGE;
113
Alexey Brodkin3cadcbd2018-11-27 09:47:00 +0300114 writel(creg_boot, CREG_BOOT);
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300115
116 return CMD_RET_SUCCESS;
117}
118
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300119cmd_tbl_t cmd_emsdp[] = {
120 U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300121};
122
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300123static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300124{
125 cmd_tbl_t *c;
126
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300127 c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300128
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300129 /* Strip off leading 'emsdp' command */
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300130 argc--;
131 argv++;
132
133 if (c == NULL || argc > c->maxargs)
134 return CMD_RET_USAGE;
135
136 return c->cmd(cmdtp, flag, argc, argv);
137}
138
139U_BOOT_CMD(
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300140 emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
141 "Synopsys EMSDP specific commands",
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300142 "rom unlock - Unlock non-volatile memory for writing\n"
Alexey Brodkinddbf6972018-10-18 09:54:58 +0300143 "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
Alexey Brodkin4b2705b2018-05-28 15:27:43 +0300144);
Alexey Brodkindbf9fa22018-11-27 09:47:01 +0300145
146int checkboard(void)
147{
148 int version = readl(CREG_IP_VERSION);
149
150 printf("Board: ARC EM Software Development Platform v%d.%d\n",
151 (version >> 16) & 0xff, version & 0xff);
152 return 0;
153};