blob: 671064fae278ccd8e89c2d1299bf0be0d5e32af1 [file] [log] [blame]
Peng Fan702c6dc2018-10-18 14:28:37 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06007#include <env.h>
Peng Fan702c6dc2018-10-18 14:28:37 +02008#include <errno.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Peng Fan702c6dc2018-10-18 14:28:37 +020010#include <linux/libfdt.h>
Yangbo Lu73340382019-06-21 11:42:28 +080011#include <fsl_esdhc_imx.h>
Peng Fan702c6dc2018-10-18 14:28:37 +020012#include <asm/io.h>
13#include <asm/gpio.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/sci/sci.h>
16#include <asm/arch/imx8-pins.h>
17#include <asm/arch/iomux.h>
18#include <asm/arch/sys_proto.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
23 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
24 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
25 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
26
27#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
28 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
29 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
30 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
31
32static iomux_cfg_t uart0_pads[] = {
33 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
34 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
35};
36
37static void setup_iomux_uart(void)
38{
39 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
40}
41
42int board_early_init_f(void)
43{
Anatolij Gustschinef156d22019-06-12 13:35:25 +020044 sc_pm_clock_rate_t rate = SC_80MHZ;
Peng Fan702c6dc2018-10-18 14:28:37 +020045 int ret;
Peng Fan702c6dc2018-10-18 14:28:37 +020046
Anatolij Gustschinef156d22019-06-12 13:35:25 +020047 /* Set UART0 clock root to 80 MHz */
48 ret = sc_pm_setup_uart(SC_R_UART_0, rate);
Peng Fan702c6dc2018-10-18 14:28:37 +020049 if (ret)
50 return ret;
51
52 setup_iomux_uart();
53
54 return 0;
55}
56
57#if IS_ENABLED(CONFIG_DM_GPIO)
58static void board_gpio_init(void)
59{
60 struct gpio_desc desc;
61 int ret;
62
63 ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
64 if (ret)
65 return;
66
67 ret = dm_gpio_request(&desc, "bb_per_rst_b");
68 if (ret)
69 return;
70
71 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
72 dm_gpio_set_value(&desc, 0);
73 udelay(50);
74 dm_gpio_set_value(&desc, 1);
75}
76#else
77static inline void board_gpio_init(void) {}
78#endif
79
80#if IS_ENABLED(CONFIG_FEC_MXC)
81#include <miiphy.h>
82
83int board_phy_config(struct phy_device *phydev)
84{
85 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
86 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
87
88 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
89 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
90
91 if (phydev->drv->config)
92 phydev->drv->config(phydev);
93
94 return 0;
95}
96#endif
97
Peng Fan702c6dc2018-10-18 14:28:37 +020098int checkboard(void)
99{
100 puts("Board: iMX8QXP MEK\n");
101
102 build_info();
103 print_bootinfo();
104
105 return 0;
106}
107
108int board_init(void)
109{
110 board_gpio_init();
111
112 return 0;
113}
114
115void detail_board_ddr_info(void)
116{
117 puts("\nDDR ");
118}
119
120/*
121 * Board specific reset that is system reset.
122 */
123void reset_cpu(ulong addr)
124{
125 /* TODO */
126}
127
128#ifdef CONFIG_OF_BOARD_SETUP
129int ft_board_setup(void *blob, bd_t *bd)
130{
131 return 0;
132}
133#endif
134
135int board_mmc_get_env_dev(int devno)
136{
137 return devno;
138}
139
140int board_late_init(void)
141{
142#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
143 env_set("board_name", "MEK");
144 env_set("board_rev", "iMX8QXP");
145#endif
146
147 return 0;
148}