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Michael Schwingen6c3297e2008-01-16 19:51:55 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * hardware register definitions for the AcTux-3 board.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingen6c3297e2008-01-16 19:51:55 +01008 */
9
10#ifndef _ACTUX3_HW_H
11#define _ACTUX3_HW_H
12
13/* 0 = LED off,1 = ON */
14#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
15#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
16#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
17#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
18#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
19#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
20#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
21#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
22
23#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
24#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
25#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
26
27/* GPIO settings */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020028#define CONFIG_SYS_GPIO_DBGINT 0
29#define CONFIG_SYS_GPIO_ETHINT 1
30#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
31#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
32#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */
33#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */
34#define CONFIG_SYS_GPIO_DSR 6 /* Out */
35#define CONFIG_SYS_GPIO_DCD 7 /* Out */
36#define CONFIG_SYS_GPIO_DBGJUMPER 9
37#define CONFIG_SYS_GPIO_BUTTON1 10
38#define CONFIG_SYS_GPIO_DBGSENSE 11
39#define CONFIG_SYS_GPIO_DTR 12
40#define CONFIG_SYS_GPIO_IORST 13 /* Out */
41#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
42#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
Michael Schwingen6c3297e2008-01-16 19:51:55 +010043
44#endif