| Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | .. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com> |
| 3 | |
| Bryan Brattlof | 10d3f17 | 2022-12-19 14:29:49 -0600 | [diff] [blame] | 4 | AM62 Platforms |
| 5 | =============== |
| Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 6 | |
| 7 | Introduction: |
| 8 | ------------- |
| 9 | The AM62 SoC family is the follow on AM335x built on the K3 Multicore |
| 10 | SoC architecture platform, providing ultra-low-power modes, dual |
| 11 | display, multi-sensor edge compute, security and other BOM-saving |
| 12 | integrations. The AM62 SoC targets a broad market to enable |
| 13 | applications such as Industrial HMI, PLC/CNC/Robot control, Medical |
| 14 | Equipment, Building Automation, Appliances and more. |
| 15 | |
| 16 | Some highlights of this SoC are: |
| 17 | |
| 18 | * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. |
| 19 | Pin-to-pin compatible options for single and quad core are available. |
| 20 | * Cortex-M4F for general-purpose or safety usage. |
| 21 | * Dual display support, providing 24-bit RBG parallel interface and |
| 22 | OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display |
| 23 | resolution. |
| 24 | * Selectable GPU support, up to 8GFLOPS, providing better user experience |
| 25 | in 3D graphic display case and Android. |
| 26 | * PRU(Programmable Realtime Unit) support for customized programmable |
| 27 | interfaces/IOs. |
| 28 | * Integrated Giga-bit Ethernet switch supporting up to a total of two |
| 29 | external ports (TSN capable). |
| 30 | * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for |
| 31 | NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, |
| 32 | 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. |
| 33 | * Dedicated Centralized System Controller for Security, Power, and |
| 34 | Resource Management. |
| 35 | * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, |
| 36 | enabling battery powered system design. |
| 37 | |
| 38 | More details can be found in the Technical Reference Manual: |
| 39 | https://www.ti.com/lit/pdf/spruiv7 |
| 40 | |
| 41 | Boot Flow: |
| 42 | ---------- |
| 43 | Below is the pictorial representation of boot flow: |
| 44 | |
| 45 | .. code-block:: text |
| 46 | |
| 47 | +------------------------------------------------------------------------+ |
| 48 | | TIFS | Main R5 | A53 | |
| 49 | +------------------------------------------------------------------------+ |
| 50 | | +--------+ | | | |
| 51 | | | Reset | | | | |
| 52 | | +--------+ | | | |
| 53 | | : | | | |
| 54 | | +--------+ | +-----------+ | | |
| 55 | | | *ROM* |----------|-->| Reset rls | | | |
| 56 | | +--------+ | +-----------+ | | |
| 57 | | | | | : | | |
| 58 | | | ROM | | : | | |
| 59 | | |services| | : | | |
| 60 | | | | | +-------------+ | | |
| 61 | | | | | | *R5 ROM* | | | |
| 62 | | | | | +-------------+ | | |
| 63 | | | |<---------|---|Load and auth| | | |
| 64 | | | | | | tiboot3.bin | | | |
| 65 | | +--------+ | +-------------+ | | |
| 66 | | | |<---------|---| Load sysfw | | | |
| 67 | | | | | | part to TIFS| | | |
| 68 | | | | | | core | | | |
| 69 | | | | | +-------------+ | | |
| 70 | | | | | : | | |
| 71 | | | | | : | | |
| 72 | | | | | : | | |
| 73 | | | | | +-------------+ | | |
| 74 | | | | | | *R5 SPL* | | | |
| 75 | | | | | +-------------+ | | |
| 76 | | | | | | DDR | | | |
| 77 | | | | | | config | | | |
| 78 | | | | | +-------------+ | | |
| 79 | | | | | | Load | | | |
| 80 | | | | | | tispl.bin | | | |
| 81 | | | | | +-------------+ | | |
| 82 | | | | | | Load R5 | | | |
| 83 | | | | | | firmware | | | |
| 84 | | | | | +-------------+ | | |
| 85 | | | |<---------|---| Start A53 | | | |
| 86 | | | | | | and jump to | | | |
| 87 | | | | | | DM fw image | | | |
| 88 | | | | | +-------------+ | | |
| 89 | | | | | | +-----------+ | |
| 90 | | | |----------|-----------------------|---->| Reset rls | | |
| 91 | | | | | | +-----------+ | |
| 92 | | | TIFS | | | : | |
| 93 | | |Services| | | +-----------+ | |
| 94 | | | |<---------|-----------------------|---->|*ATF/OPTEE*| | |
| 95 | | | | | | +-----------+ | |
| 96 | | | | | | : | |
| 97 | | | | | | +-----------+ | |
| 98 | | | |<---------|-----------------------|---->| *A53 SPL* | | |
| 99 | | | | | | +-----------+ | |
| 100 | | | | | | | Load | | |
| 101 | | | | | | | u-boot.img| | |
| 102 | | | | | | +-----------+ | |
| 103 | | | | | | : | |
| 104 | | | | | | +-----------+ | |
| 105 | | | |<---------|-----------------------|---->| *U-Boot* | | |
| 106 | | | | | | +-----------+ | |
| 107 | | | | | | | prompt | | |
| 108 | | | |----------|-----------------------|-----+-----------+-----| |
| 109 | | +--------+ | | | |
| 110 | | | | | |
| 111 | +------------------------------------------------------------------------+ |
| 112 | |
| 113 | - Here TIFS acts as master and provides all the critical services. R5/A53 |
| 114 | requests TIFS to get these services done as shown in the above diagram. |
| 115 | |
| 116 | Sources: |
| 117 | -------- |
| 118 | 1. SYSFW: |
| 119 | Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git |
| 120 | Branch: master |
| 121 | |
| 122 | 2. ATF: |
| 123 | Tree: https://github.com/ARM-software/arm-trusted-firmware.git |
| 124 | Branch: master |
| 125 | |
| 126 | 3. OPTEE: |
| 127 | Tree: https://github.com/OP-TEE/optee_os.git |
| 128 | Branch: master |
| 129 | |
| 130 | 4. U-Boot: |
| 131 | Tree: https://source.denx.de/u-boot/u-boot |
| 132 | Branch: master |
| 133 | |
| 134 | 5. TI Linux Firmware: |
| 135 | Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git |
| 136 | Branch: ti-linux-firmware |
| 137 | |
| 138 | Build procedure: |
| 139 | ---------------- |
| 140 | 1. ATF: |
| 141 | |
| 142 | .. code-block:: text |
| 143 | |
| 144 | $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=lite SPD=opteed |
| 145 | |
| 146 | 2. OPTEE: |
| 147 | |
| 148 | .. code-block:: text |
| 149 | |
| 150 | $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- CROSS_COMPILE64=aarch64-none-linux-gnu- |
| 151 | |
| 152 | 3. U-Boot: |
| 153 | |
| 154 | * 3.1 R5: |
| 155 | |
| 156 | .. code-block:: text |
| 157 | |
| 158 | $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am62x_evm_r5_defconfig O=/tmp/r5 |
| 159 | $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- O=/tmp/r5 |
| 160 | $ cd <k3-image-gen> |
| 161 | $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=<path to ti-linux-firmware>/ti-sysfw/ti-fs-firmware-am62x-gp.bin |
| 162 | |
| 163 | Use the tiboot3.bin generated from last command |
| 164 | |
| 165 | * 3.2 A53: |
| 166 | |
| 167 | .. code-block:: text |
| 168 | |
| 169 | $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- am62x_evm_a53_defconfig O=/tmp/a53 |
| 170 | $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- ATF=<path to ATF dir>/build/k3/lite/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to ti-linux-firmware>/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53 |
| 171 | |
| 172 | Target Images |
| 173 | -------------- |
| 174 | Copy the below images to an SD card and boot: |
| 175 | - tiboot3.bin from step 3.1 |
| 176 | - tispl.bin, u-boot.img from 3.2 |
| 177 | |
| 178 | Image formats: |
| 179 | -------------- |
| 180 | |
| 181 | - tiboot3.bin: |
| 182 | |
| 183 | .. code-block:: text |
| 184 | |
| 185 | +-----------------------+ |
| 186 | | X.509 | |
| 187 | | Certificate | |
| 188 | | +-------------------+ | |
| 189 | | | | | |
| 190 | | | R5 | | |
| 191 | | | u-boot-spl.bin | | |
| 192 | | | | | |
| 193 | | +-------------------+ | |
| 194 | | | | | |
| 195 | | |TIFS with board cfg| | |
| 196 | | | | | |
| 197 | | +-------------------+ | |
| 198 | | | | | |
| 199 | | | | | |
| 200 | | | FIT header | | |
| 201 | | | +---------------+ | | |
| 202 | | | | | | | |
| 203 | | | | DTB 1...N | | | |
| 204 | | | +---------------+ | | |
| 205 | | +-------------------+ | |
| 206 | +-----------------------+ |
| 207 | |
| 208 | - tispl.bin |
| 209 | |
| 210 | .. code-block:: text |
| 211 | |
| 212 | +-----------------------+ |
| 213 | | | |
| 214 | | FIT HEADER | |
| 215 | | +-------------------+ | |
| 216 | | | | | |
| 217 | | | A53 ATF | | |
| 218 | | +-------------------+ | |
| 219 | | | | | |
| 220 | | | A53 OPTEE | | |
| 221 | | +-------------------+ | |
| 222 | | | | | |
| 223 | | | R5 DM FW | | |
| 224 | | +-------------------+ | |
| 225 | | | | | |
| 226 | | | A53 SPL | | |
| 227 | | +-------------------+ | |
| 228 | | | | | |
| 229 | | | SPL DTB 1...N | | |
| 230 | | +-------------------+ | |
| 231 | +-----------------------+ |
| Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 232 | |
| Nikhil M Jain | a9b1204 | 2023-07-18 14:27:35 +0530 | [diff] [blame] | 233 | A53 SPL DDR Memory Layout |
| 234 | ------------------------- |
| 235 | |
| 236 | This provides an overview memory usage in A53 SPL stage. |
| 237 | |
| 238 | .. list-table:: |
| 239 | :widths: 16 16 16 |
| 240 | :header-rows: 1 |
| 241 | |
| 242 | * - Region |
| 243 | - Start Address |
| 244 | - End Address |
| 245 | |
| 246 | * - EMPTY |
| 247 | - 0x80000000 |
| 248 | - 0x80080000 |
| 249 | |
| 250 | * - TEXT BASE |
| 251 | - 0x80080000 |
| 252 | - 0x800d8000 |
| 253 | |
| 254 | * - EMPTY |
| 255 | - 0x800d8000 |
| 256 | - 0x80200000 |
| 257 | |
| 258 | * - BMP IMAGE |
| 259 | - 0x80200000 |
| 260 | - 0x80b77660 |
| 261 | |
| 262 | * - STACK |
| 263 | - 0x80b77660 |
| 264 | - 0x80b77e60 |
| 265 | |
| 266 | * - GD |
| 267 | - 0x80b77e60 |
| 268 | - 0x80b78000 |
| 269 | |
| 270 | * - MALLOC |
| 271 | - 0x80b78000 |
| 272 | - 0x80b80000 |
| 273 | |
| 274 | * - EMPTY |
| 275 | - 0x80b80000 |
| 276 | - 0x80c80000 |
| 277 | |
| 278 | * - BSS |
| 279 | - 0x80c80000 |
| 280 | - 0x80d00000 |
| 281 | |
| 282 | * - BLOBS |
| 283 | - 0x80d00000 |
| 284 | - 0x80d00400 |
| 285 | |
| 286 | * - EMPTY |
| 287 | - 0x80d00400 |
| 288 | - 0x81000000 |
| 289 | |
| Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 290 | Switch Setting for Boot Mode |
| 291 | ---------------------------- |
| 292 | |
| 293 | Boot Mode pins provide means to select the boot mode and options before the |
| 294 | device is powered up. After every POR, they are the main source to populate |
| 295 | the Boot Parameter Tables. |
| 296 | |
| 297 | The following table shows some common boot modes used on AM62 platform. More |
| 298 | details can be found in the Technical Reference Manual: |
| 299 | https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. |
| 300 | |
| 301 | *Boot Modes* |
| 302 | |
| 303 | ============ ============= ============= |
| 304 | Switch Label SW2: 12345678 SW3: 12345678 |
| 305 | ============ ============= ============= |
| 306 | SD 01000000 11000010 |
| 307 | OSPI 00000000 11001110 |
| 308 | EMMC 00000000 11010010 |
| 309 | UART 00000000 11011100 |
| 310 | USB DFU 00000000 11001010 |
| 311 | ============ ============= ============= |
| 312 | |
| 313 | For SW2 and SW1, the switch state in the "ON" position = 1. |