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Aubrey.Li9da597f2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 EZKIT board
3 */
4
Mike Frysinger62d2a232008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_EZKIT_H__
6#define __CONFIG_BF533_EZKIT_H__
Aubrey.Li9da597f2007-03-09 13:38:44 +08007
Mike Frysinger18a407c2009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf0dd7922008-02-18 05:26:48 -05009
Aubrey.Li9da597f2007-03-09 13:38:44 +080010
Jon Loeliger8262ada2007-07-04 22:31:49 -050011/*
Mike Frysinger62d2a232008-06-01 09:09:48 -040012 * Processor Settings
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050013 */
Mike Frysinger62d2a232008-06-01 09:09:48 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050015
16
17/*
Mike Frysinger62d2a232008-06-01 09:09:48 -040018 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
Jon Loeliger8262ada2007-07-04 22:31:49 -050021 */
Mike Frysinger62d2a232008-06-01 09:09:48 -040022/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 27000000
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
32#define CONFIG_VCO_MULT 22
33/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
38#define CONFIG_SCLK_DIV 5
Aubrey.Li9da597f2007-03-09 13:38:44 +080039
Jon Loeliger8262ada2007-07-04 22:31:49 -050040
Mike Frysinger62d2a232008-06-01 09:09:48 -040041/*
42 * Memory Settings
43 */
44#define CONFIG_MEM_SIZE 32
45/* Early EZKITs had 32megs, but later have 64megs */
46#if (CONFIG_MEM_SIZE == 64)
47# define CONFIG_MEM_ADD_WDTH 10
Aubrey.Li9da597f2007-03-09 13:38:44 +080048#else
Mike Frysinger62d2a232008-06-01 09:09:48 -040049# define CONFIG_MEM_ADD_WDTH 9
Aubrey.Li9da597f2007-03-09 13:38:44 +080050#endif
Aubrey.Li9da597f2007-03-09 13:38:44 +080051
Mike Frysinger62d2a232008-06-01 09:09:48 -040052#define CONFIG_EBIU_SDRRC_VAL 0x398
53#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
Aubrey.Li9da597f2007-03-09 13:38:44 +080054
Mike Frysinger62d2a232008-06-01 09:09:48 -040055#define CONFIG_EBIU_AMGCTL_VAL 0xFF
56#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
57#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
Aubrey.Li9da597f2007-03-09 13:38:44 +080058
Mike Frysinger62d2a232008-06-01 09:09:48 -040059#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
60#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
Aubrey.Li9da597f2007-03-09 13:38:44 +080061
62
63/*
Mike Frysinger62d2a232008-06-01 09:09:48 -040064 * Network Settings
Aubrey.Li9da597f2007-03-09 13:38:44 +080065 */
Mike Frysinger62d2a232008-06-01 09:09:48 -040066#define ADI_CMDS_NETWORK 1
Ben Warren0fd6aae2009-10-04 22:37:03 -070067#define CONFIG_NET_MULTI
68#define CONFIG_SMC91111 1
Mike Frysinger62d2a232008-06-01 09:09:48 -040069#define CONFIG_SMC91111_BASE 0x20310300
70#define SMC91111_EEPROM_INIT() \
71 do { \
Ben Warren0fd6aae2009-10-04 22:37:03 -070072 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
73 bfin_write_FIO_FLAG_C(PF1); \
74 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysinger62d2a232008-06-01 09:09:48 -040075 SSYNC(); \
76 } while (0)
77#define CONFIG_HOSTNAME bf533-ezkit
78/* Uncomment next line to use fixed MAC address */
79/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Aubrey.Li9da597f2007-03-09 13:38:44 +080080
Aubrey.Li9da597f2007-03-09 13:38:44 +080081
82/*
Mike Frysinger62d2a232008-06-01 09:09:48 -040083 * Flash Settings
Aubrey.Li9da597f2007-03-09 13:38:44 +080084 */
Mike Frysinger62d2a232008-06-01 09:09:48 -040085#define CONFIG_SYS_FLASH_BASE 0x20000000
86#define CONFIG_SYS_MAX_FLASH_BANKS 3
87#define CONFIG_SYS_MAX_FLASH_SECT 40
88#define CONFIG_ENV_IS_IN_FLASH
Mike Frysingerce6b6c82009-09-21 18:04:49 -040089#define CONFIG_ENV_ADDR 0x20030000
Mike Frysinger62d2a232008-06-01 09:09:48 -040090#define CONFIG_ENV_SECT_SIZE 0x10000
91#define FLASH_TOT_SECT 40
92
Aubrey.Li9da597f2007-03-09 13:38:44 +080093
94/*
Mike Frysinger62d2a232008-06-01 09:09:48 -040095 * I2C Settings
Aubrey.Li9da597f2007-03-09 13:38:44 +080096 */
Mike Frysinger62d2a232008-06-01 09:09:48 -040097#define CONFIG_SOFT_I2C
Mike Frysingerd86e9a72010-06-08 16:22:44 -040098#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
99#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
Aubrey.Li9da597f2007-03-09 13:38:44 +0800100
Aubrey.Li9da597f2007-03-09 13:38:44 +0800101
Mike Frysinger62d2a232008-06-01 09:09:48 -0400102/*
103 * Misc Settings
104 */
105#define CONFIG_MISC_INIT_R
106#define CONFIG_RTC_BFIN
107#define CONFIG_UART_CONSOLE 0
108
Aubrey.Li9da597f2007-03-09 13:38:44 +0800109
Mike Frysinger62d2a232008-06-01 09:09:48 -0400110/*
111 * Pull in common ADI header for remaining command/environment setup
112 */
113#include <configs/bfin_adi_common.h>
Aubrey.Li9da597f2007-03-09 13:38:44 +0800114
Aubrey.Li9da597f2007-03-09 13:38:44 +0800115#endif