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git01.mediatek.com / filogic / uboot / 5f1a11ee50c2d13d618865fe20239c117aefc07d / . / configs / chromebook_kevin_defconfig
blob: bc0e89d0e367b67a2e7e3c9eba888b8430882d5f [file] [log] [blame]
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]5CONFIG_TEXT_BASE=0x00200000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]6CONFIG_SPL_GPIO=y
7CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]10CONFIG_ENV_OFFSET=0x3F8000
11CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
12CONFIG_SPL_TEXT_BASE=0xff8c2000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]13CONFIG_DM_RESET=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]14CONFIG_ROCKCHIP_RK3399=y
15CONFIG_ROCKCHIP_BOOT_MODE_REG=0
16CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
17# CONFIG_SPL_MMC is not set
18CONFIG_TARGET_CHROMEBOOK_KEVIN=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]19CONFIG_SPL_STACK=0xff8effff
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]20CONFIG_DEBUG_UART_BASE=0xff1a0000
21CONFIG_DEBUG_UART_CLOCK=24000000
22CONFIG_SPL_SPI_FLASH_SUPPORT=y
23CONFIG_SPL_SPI=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]24CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]25CONFIG_DEBUG_UART=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]26CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
27# CONFIG_DISPLAY_CPUINFO is not set
28CONFIG_DISPLAY_BOARDINFO_LATE=y
29CONFIG_BOARD_EARLY_INIT_R=y
30CONFIG_MISC_INIT_R=y
31CONFIG_BLOBLIST=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]32CONFIG_BLOBLIST_ADDR=0x100000
Tom Rini8f84e4e2022-03-28 14:01:11 +0000[diff] [blame]33CONFIG_BLOBLIST_SIZE=0x1000
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]34CONFIG_SPL_MAX_SIZE=0x2e000
35CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]36CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
37CONFIG_SPL_BSS_START_ADDR=0xff8e0000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]38CONFIG_SPL_BSS_MAX_SIZE=0x10000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]39CONFIG_HANDOFF=y
40# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]41# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]42CONFIG_SPL_STACK_R=y
43CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
44CONFIG_SPL_SPI_LOAD=y
45CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
46CONFIG_CMD_BOOTZ=y
47CONFIG_CMD_GPIO=y
48CONFIG_CMD_GPT=y
49CONFIG_CMD_I2C=y
50CONFIG_CMD_MMC=y
51CONFIG_CMD_SF_TEST=y
52CONFIG_CMD_SPI=y
53CONFIG_CMD_USB=y
54# CONFIG_CMD_SETEXPR is not set
55CONFIG_CMD_TIME=y
56CONFIG_CMD_PMIC=y
57CONFIG_CMD_REGULATOR=y
58CONFIG_CMD_LOG=y
59CONFIG_SPL_OF_CONTROL=y
60CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
61CONFIG_ENV_IS_IN_MMC=y
62CONFIG_SYS_RELOC_GD_ENV_ADDR=y
63CONFIG_SPL_DM_SEQ_ALIAS=y
64CONFIG_ROCKCHIP_GPIO=y
65CONFIG_I2C_CROS_EC_TUNNEL=y
66CONFIG_SYS_I2C_ROCKCHIP=y
67CONFIG_I2C_MUX=y
68CONFIG_CROS_EC_KEYB=y
69CONFIG_MISC=y
70CONFIG_ROCKCHIP_EFUSE=y
71CONFIG_CROS_EC=y
72CONFIG_CROS_EC_SPI=y
73CONFIG_PWRSEQ=y
74CONFIG_MMC_PWRSEQ=y
75CONFIG_MMC_DW=y
76CONFIG_MMC_DW_ROCKCHIP=y
77CONFIG_MMC_SDHCI=y
78CONFIG_MMC_SDHCI_ROCKCHIP=y
79CONFIG_SF_DEFAULT_BUS=1
80CONFIG_SF_DEFAULT_SPEED=20000000
81CONFIG_SPI_FLASH_GIGADEVICE=y
82CONFIG_SPI_FLASH_WINBOND=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]83CONFIG_ETH_DESIGNWARE=y
84CONFIG_GMAC_ROCKCHIP=y
85CONFIG_PHY_ROCKCHIP_INNO_USB2=y
86CONFIG_PHY_ROCKCHIP_TYPEC=y
87CONFIG_PMIC_RK8XX=y
88CONFIG_REGULATOR_PWM=y
89CONFIG_DM_REGULATOR_GPIO=y
90CONFIG_REGULATOR_RK8XX=y
91CONFIG_PWM_CROS_EC=y
92CONFIG_PWM_ROCKCHIP=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]93CONFIG_DM_RNG=y
94CONFIG_RNG_ROCKCHIP=y
95CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]96CONFIG_SYS_NS16550_MEM32=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]97CONFIG_ROCKCHIP_SPI=y
98CONFIG_SYSRESET=y
99CONFIG_USB=y
100CONFIG_USB_XHCI_HCD=y
101CONFIG_USB_XHCI_DWC3=y
102CONFIG_USB_EHCI_HCD=y
103CONFIG_USB_EHCI_GENERIC=y
104CONFIG_USB_OHCI_HCD=y
105CONFIG_USB_OHCI_GENERIC=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]106CONFIG_USB_DWC3=y
107CONFIG_USB_KEYBOARD=y
108CONFIG_USB_HOST_ETHER=y
109CONFIG_USB_ETHER_ASIX=y
110CONFIG_USB_ETHER_ASIX88179=y
111CONFIG_USB_ETHER_MCS7830=y
112CONFIG_USB_ETHER_RTL8152=y
113CONFIG_USB_ETHER_SMSC95XX=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]114CONFIG_VIDEO=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]115CONFIG_DISPLAY=y
116CONFIG_VIDEO_ROCKCHIP=y
117CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
118CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
119CONFIG_DISPLAY_ROCKCHIP_EDP=y
120CONFIG_CMD_DHRYSTONE=y
121CONFIG_ERRNO_STR=y