blob: a89c69a72b5158cc0aa74625b5ac9e4cb2955533 [file] [log] [blame]
Andreas Färber9e3ad682017-05-15 17:51:18 +08001/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_RK3368_COMMON_H
8#define __CONFIG_RK3368_COMMON_H
9
10#define CONFIG_SYS_CACHELINE_SIZE 64
11
12#include <asm/arch/hardware.h>
13#include <linux/sizes.h>
14
Kever Yang5db9e672017-06-23 16:11:05 +080015#define CONFIG_SYS_SDRAM_BASE 0
16#define SDRAM_MAX_SIZE 0xff000000
Andreas Färber9e3ad682017-05-15 17:51:18 +080017#define CONFIG_NR_DRAM_BANKS 1
18#define CONFIG_SYS_MAXARGS 16
19#define CONFIG_BAUDRATE 115200
20#define CONFIG_SYS_MALLOC_LEN (32 << 20)
21#define CONFIG_SYS_CBSIZE 1024
22#define CONFIG_SKIP_LOWLEVEL_INIT
23
Philipp Tomsich9b687c72017-06-22 23:31:55 +020024#define COUNTER_FREQUENCY 24000000
25
Philipp Tomsichc46382b2017-07-14 17:51:44 +020026#define CONFIG_SPL_FRAMEWORK
Andreas Färber9e3ad682017-05-15 17:51:18 +080027#define CONFIG_SYS_NS16550_MEM32
28
29#define CONFIG_SYS_TEXT_BASE 0x00200000
30#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
31#define CONFIG_SYS_LOAD_ADDR 0x00280000
32
Philipp Tomsich0c1c09f2017-07-14 17:52:09 +020033#define CONFIG_SPL_TEXT_BASE 0x00000000
34#define CONFIG_SPL_MAX_SIZE 0x40000
35#define CONFIG_SPL_BSS_START_ADDR 0x400000
36#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
37
Andreas Färber9e3ad682017-05-15 17:51:18 +080038#define CONFIG_BOUNCE_BUFFER
39
40#ifndef CONFIG_SPL_BUILD
41#define ENV_MEM_LAYOUT_SETTINGS \
42 "scriptaddr=0x00500000\0" \
43 "pxefile_addr_r=0x00600000\0" \
44 "fdt_addr_r=0x5600000\0" \
45 "kernel_addr_r=0x280000\0" \
46 "ramdisk_addr_r=0x5bf0000\0"
47
48#include <config_distro_defaults.h>
49
50#define BOOT_TARGET_DEVICES(func)
51
52#include <config_distro_bootcmd.h>
53
54#define CONFIG_EXTRA_ENV_SETTINGS \
55 BOOTENV
56
57#endif
58
59#endif