| Manivannan Sadhasivam | 91a8513 | 2018-06-14 23:38:35 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Actions Semi S900 Clock Definitions |
| 4 | * |
| 5 | * Copyright (C) 2015 Actions Semi Co., Ltd. |
| 6 | * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #ifndef _OWL_CLK_S900_H_ |
| 11 | #define _OWL_CLK_S900_H_ |
| 12 | |
| 13 | #include <clk-uclass.h> |
| 14 | |
| 15 | struct owl_clk_priv { |
| 16 | phys_addr_t base; |
| 17 | }; |
| 18 | |
| 19 | /* BUSCLK register definitions */ |
| 20 | #define CMU_PDBGDIV_8 7 |
| 21 | #define CMU_PDBGDIV_SHIFT 26 |
| 22 | #define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) |
| 23 | #define CMU_PERDIV_8 7 |
| 24 | #define CMU_PERDIV_SHIFT 20 |
| 25 | #define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) |
| 26 | #define CMU_NOCDIV_2 1 |
| 27 | #define CMU_NOCDIV_SHIFT 19 |
| 28 | #define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) |
| 29 | #define CMU_DMMCLK_SRC_APLL 2 |
| 30 | #define CMU_DMMCLK_SRC_SHIFT 10 |
| 31 | #define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) |
| 32 | #define CMU_APBCLK_DIV BIT(8) |
| 33 | #define CMU_NOCCLK_SRC BIT(7) |
| 34 | #define CMU_AHBCLK_DIV BIT(4) |
| 35 | #define CMU_CORECLK_MASK 3 |
| 36 | #define CMU_CORECLK_CPLL BIT(1) |
| 37 | #define CMU_CORECLK_HOSC BIT(0) |
| 38 | |
| 39 | /* COREPLL register definitions */ |
| 40 | #define CMU_COREPLL_EN BIT(9) |
| 41 | #define CMU_COREPLL_HOSC_EN BIT(8) |
| 42 | #define CMU_COREPLL_OUT (1104 / 24) |
| 43 | |
| 44 | /* DEVPLL register definitions */ |
| 45 | #define CMU_DEVPLL_CLK BIT(12) |
| 46 | #define CMU_DEVPLL_EN BIT(8) |
| 47 | #define CMU_DEVPLL_OUT (660 / 6) |
| 48 | |
| 49 | /* UARTCLK register definitions */ |
| 50 | #define CMU_UARTCLK_SRC_DEVPLL BIT(16) |
| 51 | |
| 52 | /* DEVCLKEN1 register definitions */ |
| 53 | #define CMU_DEVCLKEN1_UART5 BIT(21) |
| 54 | |
| 55 | #define PLL_STABILITY_WAIT_US 50 |
| 56 | |
| 57 | #endif |