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git01.mediatek.com / filogic / uboot / 5e8f4ad2836a7adf7414b8c58ca2a50e4f181169 / . / arch / arm / dts / imxrt1020.dtsi
blob: 97f3cec9f3d222120ba627f0eb7276a6317e54a4 [file] [log] [blame]
Giulio Benettie228d222020-02-18 20:02:53 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2020
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/imxrt1020-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/memory/imxrt-sdram.h>
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 mmc0 = &usdhc1;
22 serial0 = &lpuart1;
23 };
24
25 clocks {
26 u-boot,dm-spl;
27 ckil {
28 compatible = "fsl,imx-ckil", "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 };
32
33 ckih1 {
34 compatible = "fsl,imx-ckih1", "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 };
38
39 osc {
40 u-boot,dm-spl;
41 compatible = "fsl,imx-osc", "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <24000000>;
44 };
45 };
46
47 soc {
48 u-boot,dm-spl;
49
50 semc: semc@402f0000 {
51 u-boot,dm-spl;
52 compatible = "fsl,imxrt-semc";
53 reg = <0x402f0000 0x4000>;
54 clocks = <&clks IMXRT1020_CLK_SEMC>;
55 pinctrl-0 = <&pinctrl_semc>;
56 pinctrl-names = "default";
57 status = "okay";
58 };
59
60 lpuart1: serial@40184000 {
61 compatible = "fsl,imxrt-lpuart";
62 reg = <0x40184000 0x4000>;
63 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&clks IMXRT1020_CLK_LPUART1>;
65 clock-names = "per";
66 status = "disabled";
67 };
68
69 iomuxc: iomuxc@401f8000 {
70 compatible = "fsl,imxrt-iomuxc";
71 reg = <0x401f8000 0x4000>;
72 fsl,mux_mask = <0x7>;
73 };
74
75 clks: ccm@400fc000 {
76 u-boot,dm-spl;
77 compatible = "fsl,imxrt1020-ccm";
78 reg = <0x400fc000 0x4000>;
79 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
81 #clock-cells = <1>;
82 };
83
84 usdhc1: usdhc@402c0000 {
85 u-boot,dm-spl;
86 compatible = "fsl,imxrt-usdhc";
87 reg = <0x402c0000 0x10000>;
88 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&clks IMXRT1020_CLK_USDHC1>;
90 clock-names = "per";
91 bus-width = <4>;
92 fsl,tuning-start-tap = <20>;
93 fsl,tuning-step= <2>;
94 status = "disabled";
95 };
96
97 gpio1: gpio@401b8000 {
98 u-boot,dm-spl;
99 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
100 reg = <0x401b8000 0x4000>;
101 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 };
108
109 gpio2: gpio@401bc000 {
110 u-boot,dm-spl;
111 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
112 reg = <0x401bc000 0x4000>;
113 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 gpio3: gpio@401c0000 {
122 u-boot,dm-spl;
123 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
124 reg = <0x401c0000 0x4000>;
125 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 };
132 };
133};