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git01.mediatek.com / filogic / uboot / 5e8f4ad2836a7adf7414b8c58ca2a50e4f181169 / . / arch / arm / dts / imx6ull-colibri.dtsi
blob: b7bf79f28cb68963facaa00cfd9331f1015024f6 [file] [log] [blame]
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include "imx6ull.dtsi"
9
10/ {
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]11 chosen {
12 stdout-path = &uart1;
13 };
14
15 reg_module_3v3: regulator-module-3v3 {
16 compatible = "regulator-fixed";
17 regulator-always-on;
18 regulator-name = "+V3.3";
19 regulator-min-microvolt = <3300000>;
20 regulator-max-microvolt = <3300000>;
21 };
22
23 reg_module_3v3_avdd: regulator-module-3v3-avdd {
24 compatible = "regulator-fixed";
25 regulator-always-on;
26 regulator-name = "+V3.3_AVDD_AUDIO";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 };
30
31 reg_5v0: regulator-5v0 {
32 compatible = "regulator-fixed";
33 regulator-name = "5V";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 };
37
38 reg_sd1_vmmc: regulator-sd1-vmmc {
39 compatible = "regulator-gpio";
40 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
43 regulator-always-on;
44 regulator-name = "+V3.3_1.8_SD";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <3300000>;
47 states = <1800000 0x1 3300000 0x0>;
48 vin-supply = <&reg_module_3v3>;
49 };
50
51 reg_usbh_vbus: regulator-usbh-vbus {
52 compatible = "regulator-fixed";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_usbh_reg>;
55 regulator-name = "VCC_USB[1-4]";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
59 vin-supply = <&reg_5v0>;
60 };
61};
62
63&adc1 {
64 num-channels = <10>;
65 vref-supply = <&reg_module_3v3_avdd>;
66};
67
68/* Colibri SPI */
69&ecspi1 {
70 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
73};
74
75/* Ethernet */
76&fec2 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_enet2>;
79 phy-mode = "rmii";
80 phy-handle = <&ethphy1>;
81 status = "okay";
82
83 mdio {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 ethphy1: ethernet-phy@2 {
88 compatible = "ethernet-phy-ieee802.3-c22";
89 max-speed = <100>;
90 reg = <2>;
91 };
92 };
93};
94
95/* NAND */
96&gpmi {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpmi_nand>;
99 nand-on-flash-bbt;
100 nand-ecc-mode = "hw";
101 nand-ecc-strength = <8>;
102 nand-ecc-step-size = <512>;
103 status = "okay";
104};
105
106/*
107 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
108 */
109&i2c1 {
110 pinctrl-names = "default", "gpio";
111 pinctrl-0 = <&pinctrl_i2c1>;
112 pinctrl-1 = <&pinctrl_i2c1_gpio>;
113 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 status = "okay";
116};
117
118/*
119 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
120 * touch screen controller
121 */
122&i2c2 {
123 pinctrl-names = "default", "gpio";
124 pinctrl-0 = <&pinctrl_i2c2>;
125 pinctrl-1 = <&pinctrl_i2c2_gpio>;
126 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
127 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
128 status = "okay";
129
130 ad7879@2c {
131 compatible = "adi,ad7879-1";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
134 reg = <0x2c>;
135 interrupt-parent = <&gpio5>;
136 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
137 touchscreen-max-pressure = <4096>;
138 adi,resistance-plate-x = <120>;
139 adi,first-conversion-delay = /bits/ 8 <3>;
140 adi,acquisition-time = /bits/ 8 <1>;
141 adi,median-filter-size = /bits/ 8 <2>;
142 adi,averaging = /bits/ 8 <1>;
143 adi,conversion-interval = /bits/ 8 <255>;
144 };
145};
146
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]147/* PWM <A> */
148&pwm4 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_pwm4>;
151 #pwm-cells = <3>;
152};
153
154/* PWM <B> */
155&pwm5 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_pwm5>;
158 #pwm-cells = <3>;
159};
160
161/* PWM <C> */
162&pwm6 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_pwm6>;
165 #pwm-cells = <3>;
166};
167
168/* PWM <D> */
169&pwm7 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_pwm7>;
172 #pwm-cells = <3>;
173};
174
175&sdma {
176 status = "okay";
177};
178
179&snvs_pwrkey {
180 status = "disabled";
181};
182
183/* Colibri UART_A */
184&uart1 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
187 uart-has-rtscts;
188 fsl,dte-mode;
189 status = "okay";
190};
191
192/* Colibri UART_B */
193&uart2 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart2>;
196 uart-has-rtscts;
197 fsl,dte-mode;
198};
199
200/* Colibri UART_C */
201&uart5 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart5>;
204 fsl,dte-mode;
205};
206
207/* Colibri USBC */
208&usbotg1 {
209 dr_mode = "host";
210 srp-disable;
211 hnp-disable;
212 adp-disable;
213 status = "okay";
214};
215
216/* Colibri USBH */
217&usbotg2 {
218 dr_mode = "host";
219 vbus-supply = <&reg_usbh_vbus>;
220 status = "okay";
221};
222
223/* Colibri MMC */
224&usdhc1 {
225 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
226 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
227 assigned-clock-rates = <0>, <198000000>;
228 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
229 pinctrl-names = "default", "state_100mhz", "state_200mhz";
230 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
231 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
232 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
233 vmmc-supply = <&reg_sd1_vmmc>;
234 status = "okay";
235};
236
237&iomuxc {
238 pinctrl_can_int: canint-grp {
239 fsl,pins = <
240 /* SODIMM 73 */
241 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
242 >;
243 };
244
245 pinctrl_enet2: enet2-grp {
246 fsl,pins = <
247 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
248 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
249 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
250 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
251 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
252 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
253 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
254 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
255 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
256 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
257 >;
258 };
259
260 pinctrl_ecspi1_cs: ecspi1-cs-grp {
261 fsl,pins = <
262 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
263 >;
264 };
265
266 pinctrl_ecspi1: ecspi1-grp {
267 fsl,pins = <
268 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
269 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
270 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
271 >;
272 };
273
274 pinctrl_flexcan2: flexcan2-grp {
275 fsl,pins = <
276 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
277 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
278 >;
279 };
280
281 pinctrl_gpio_bl_on: gpio-bl-on-grp {
282 fsl,pins = <
283 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
284 >;
285 };
286
287 pinctrl_gpio1: gpio1-grp {
288 fsl,pins = <
289 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
290 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
291 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
292 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
293 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
294 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
295 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
296 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
297 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
298 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
299 >;
300 };
301
302 pinctrl_gpio2: gpio2-grp { /* Camera */
303 fsl,pins = <
304 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
305 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
306 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
307 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
308 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
309 >;
310 };
311
312 pinctrl_gpio3: gpio3-grp { /* CAN2 */
313 fsl,pins = <
314 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
315 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
316 >;
317 };
318
319 pinctrl_gpio4: gpio4-grp {
320 fsl,pins = <
321 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
322 >;
323 };
324
325 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
326 fsl,pins = <
327 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
328 >;
329 };
330
331 pinctrl_gpio6: gpio6-grp { /* Wifi pins */
332 fsl,pins = <
333 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
334 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
335 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
336 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
337 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
338 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
339 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
340 >;
341 };
342
343 pinctrl_gpmi_nand: gpmi-nand-grp {
344 fsl,pins = <
345 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
346 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
347 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
348 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
349 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
350 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
351 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
352 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
353 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
354 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
355 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
356 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
357 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
358 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
359 >;
360 };
361
362 pinctrl_i2c1: i2c1-grp {
363 fsl,pins = <
364 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
365 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
366 >;
367 };
368
369 pinctrl_i2c1_gpio: i2c1-gpio-grp {
370 fsl,pins = <
371 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
372 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
373 >;
374 };
375
376 pinctrl_i2c2: i2c2-grp {
377 fsl,pins = <
378 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
379 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
380 >;
381 };
382
383 pinctrl_i2c2_gpio: i2c2-gpio-grp {
384 fsl,pins = <
385 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
386 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
387 >;
388 };
389
390 pinctrl_lcdif_dat: lcdif-dat-grp {
391 fsl,pins = <
392 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
393 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
394 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
395 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
396 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
397 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
398 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
399 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
400 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
401 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
402 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
403 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
404 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
405 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
406 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
407 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
408 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
409 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
410 >;
411 };
412
413 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
414 fsl,pins = <
415 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
416 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
417 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
418 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
419 >;
420 };
421
422 pinctrl_pwm4: pwm4-grp {
423 fsl,pins = <
424 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
425 >;
426 };
427
428 pinctrl_pwm5: pwm5-grp {
429 fsl,pins = <
430 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
431 >;
432 };
433
434 pinctrl_pwm6: pwm6-grp {
435 fsl,pins = <
436 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
437 >;
438 };
439
440 pinctrl_pwm7: pwm7-grp {
441 fsl,pins = <
442 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
443 >;
444 };
445
446 pinctrl_uart1: uart1-grp {
447 fsl,pins = <
448 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
449 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
450 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
451 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
452 >;
453 };
454
455 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
456 fsl,pins = <
457 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
458 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
459 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
460 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
461 >;
462 };
463
464 pinctrl_uart2: uart2-grp {
465 fsl,pins = <
466 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
467 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
468 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
469 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
470 >;
471 };
472 pinctrl_uart5: uart5-grp {
473 fsl,pins = <
474 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
475 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
476 >;
477 };
478
479 pinctrl_usbh_reg: gpio-usbh-reg {
480 fsl,pins = <
481 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
482 >;
483 };
484
485 pinctrl_usdhc1: usdhc1-grp {
486 fsl,pins = <
487 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
488 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
489 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
490 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
491 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
492 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
493 >;
494 };
495
496 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
497 fsl,pins = <
498 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
499 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
500 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
501 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
502 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
503 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
504 >;
505 };
506
507 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
508 fsl,pins = <
509 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
510 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
511 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
512 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
513 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
514 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
515 >;
516 };
517
518 pinctrl_usdhc2: usdhc2-grp {
519 fsl,pins = <
520 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
521 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
522 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
523 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
524 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
525 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
526
527 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
528 >;
529 };
530};
531
532&iomuxc_snvs {
533 pinctrl_snvs_gpio1: snvs-gpio1-grp {
534 fsl,pins = <
535 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
536 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
537 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
538 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
539 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
540 >;
541 };
542
543 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
544 fsl,pins = <
545 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
546 >;
547 };
548
549 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
550 fsl,pins = <
551 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
552 >;
553 };
554
555 pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
556 fsl,pins = <
557 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
558 >;
559 };
560
561 pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
562 fsl,pins = <
563 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
564 >;
565 };
566
567 pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
568 fsl,pins = <
569 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
570 >;
571 };
572
573 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
574 fsl,pins = <
575 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
576 >;
577 };
578
579 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
580 fsl,pins = <
581 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
582 >;
583 };
584
585 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
586 fsl,pins = <
587 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
588 >;
589 };
590};