dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ SMARC Carrier-II Board.
 *
 * Copyright (C) 2023 Renesas Electronics Corp.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

/ {
	aliases {
		i2c0 = &i2c0;
		serial3 = &scif0;
		mmc1 = &sdhi1;
	};

	chosen {
		bootargs = "ignore_loglevel";
		stdout-path = "serial3:115200n8";
	};

	keys {
		compatible = "gpio-keys";

		key-1 {
			interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
			linux,code = <KEY_1>;
			label = "USER_SW1";
			wakeup-source;
			debounce-interval = <20>;
		};

		key-2 {
			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
			linux,code = <KEY_2>;
			label = "USER_SW2";
			wakeup-source;
			debounce-interval = <20>;
		};

		key-3 {
			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
			linux,code = <KEY_3>;
			label = "USER_SW3";
			wakeup-source;
			debounce-interval = <20>;
		};
	};

	snd_rzg3s: sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&cpu_dai>;
		simple-audio-card,frame-master = <&cpu_dai>;
		simple-audio-card,mclk-fs = <256>;

		cpu_dai: simple-audio-card,cpu {
			sound-dai = <&ssi3>;
		};

		codec_dai: simple-audio-card,codec {
			sound-dai = <&da7212>;
			clocks = <&versa3 1>;
		};
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
		compatible = "regulator-fixed";
		regulator-name = "SDHI1 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
		compatible = "regulator-gpio";
		regulator-name = "SDHI1 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};
};

&audio_clk2 {
	clock-frequency = <12288000>;
};

&i2c0 {
	status = "okay";

	clock-frequency = <1000000>;

	da7212: codec@1a {
		compatible = "dlg,da7212";
		reg = <0x1a>;

		clocks = <&versa3 1>;
		clock-names = "mclk";

		#sound-dai-cells = <0>;

		dlg,micbias1-lvl = <2500>;
		dlg,micbias2-lvl = <2500>;
		dlg,dmic-data-sel = "lrise_rfall";
		dlg,dmic-samplephase = "between_clkedge";
		dlg,dmic-clkrate = <3000000>;

		VDDA-supply = <&reg_1p8v>;
		VDDSP-supply = <&reg_3p3v>;
		VDDMIC-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_1p8v>;
	};
};

&i2c1 {
	status = "okay";

	clock-frequency = <400000>;

	power-monitor@44 {
		compatible = "renesas,isl28022";
		reg = <0x44>;
		shunt-resistor-micro-ohms = <8000>;
		renesas,average-samples = <32>;
	};
};

&pinctrl {
	audio_clock_pins: audio-clock {
		pins = "AUDIO_CLK1", "AUDIO_CLK2";
		input-enable;
	};

	key-1-gpio-hog {
		gpio-hog;
		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
		input;
		line-name = "key-1-gpio-irq";
	};

	key-2-gpio-hog {
		gpio-hog;
		gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
		input;
		line-name = "key-2-gpio-irq";
	};

	key-3-gpio-hog {
		gpio-hog;
		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
		input;
		line-name = "key-3-gpio-irq";
	};

	scif0_pins: scif0 {
		pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
			 <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
	};

	sdhi1_pins: sd1 {
		data {
			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
			power-source = <3300>;
		};

		ctrl {
			pins = "SD1_CLK", "SD1_CMD";
			power-source = <3300>;
		};

		cd {
			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
		};
	};

	sdhi1_pins_uhs: sd1-uhs {
		data {
			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
			power-source = <1800>;
		};

		ctrl {
			pins = "SD1_CLK", "SD1_CMD";
			power-source = <1800>;
		};

		cd {
			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
		};
	};

	ssi3_pins: ssi3 {
		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
	};
};

&scif0 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif0_pins>;
	status = "okay";
};

&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";
	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	max-frequency = <125000000>;
	status = "okay";
};

&ssi3 {
	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
		 <&versa3 2>, <&audio_clk2>;
	pinctrl-names = "default";
	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
	status = "okay";
};