| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ |
| 2 | /* |
| 3 | * Copyright 2024 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __DTS_IMX95_PINFUNC_H |
| 7 | #define __DTS_IMX95_PINFUNC_H |
| 8 | |
| 9 | /* |
| 10 | * The pin function ID is a tuple of |
| 11 | * <mux_reg conf_reg input_reg mux_mode input_val> |
| 12 | */ |
| 13 | #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00 |
| 14 | #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00 |
| 15 | #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00 |
| 16 | #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00 |
| 17 | #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00 |
| 18 | #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00 |
| 19 | #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00 |
| 20 | |
| 21 | #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00 |
| 22 | #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00 |
| 23 | #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00 |
| 24 | #define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x0004 0x0208 0x0000 0x05 0x00 |
| 25 | #define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0208 0x0000 0x06 0x00 |
| 26 | |
| 27 | #define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x020C 0x060C 0x00 0x00 |
| 28 | #define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x0008 0x020C 0x044C 0x02 0x00 |
| 29 | #define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x0008 0x020C 0x0460 0x04 0x00 |
| 30 | #define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x0008 0x020C 0x0000 0x05 0x00 |
| 31 | #define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x020C 0x056C 0x06 0x00 |
| 32 | |
| 33 | #define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x0210 0x0000 0x00 0x00 |
| 34 | #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x0210 0x0000 0x01 0x00 |
| 35 | #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x000C 0x0210 0x0000 0x02 0x00 |
| 36 | #define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x0210 0x0444 0x03 0x00 |
| 37 | #define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x000C 0x0210 0x0464 0x04 0x00 |
| 38 | #define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x000C 0x0210 0x0000 0x05 0x00 |
| 39 | #define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x0210 0x0574 0x06 0x00 |
| 40 | |
| 41 | #define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x0010 0x0214 0x0000 0x00 0x00 |
| 42 | #define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x0214 0x0504 0x11 0x00 |
| 43 | #define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0214 0x0000 0x04 0x00 |
| 44 | #define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0214 0x0574 0x05 0x01 |
| 45 | #define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0214 0x0514 0x16 0x00 |
| 46 | #define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x0010 0x0214 0x0468 0x07 0x00 |
| 47 | |
| 48 | #define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x0014 0x0218 0x0000 0x00 0x00 |
| 49 | #define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x0218 0x0500 0x11 0x00 |
| 50 | #define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0218 0x0000 0x04 0x00 |
| 51 | #define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0218 0x0570 0x05 0x01 |
| 52 | #define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0218 0x0510 0x16 0x00 |
| 53 | #define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x0014 0x0218 0x046C 0x07 0x00 |
| 54 | |
| 55 | #define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x0018 0x021C 0x0000 0x00 0x00 |
| 56 | #define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x021C 0x050C 0x11 0x00 |
| 57 | #define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x021C 0x0000 0x04 0x00 |
| 58 | #define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x021C 0x056C 0x05 0x01 |
| 59 | #define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x021C 0x051C 0x16 0x00 |
| 60 | #define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x0018 0x021C 0x0470 0x07 0x00 |
| 61 | |
| 62 | #define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x001C 0x0220 0x0000 0x00 0x00 |
| 63 | #define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x0220 0x0508 0x11 0x00 |
| 64 | #define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x0220 0x0000 0x04 0x00 |
| 65 | #define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x0220 0x0000 0x05 0x00 |
| 66 | #define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x0220 0x0518 0x16 0x00 |
| 67 | #define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x001C 0x0220 0x0474 0x07 0x00 |
| 68 | |
| 69 | #define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x0020 0x0224 0x0000 0x00 0x00 |
| 70 | #define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0224 0x0000 0x01 0x00 |
| 71 | #define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0224 0x0000 0x02 0x00 |
| 72 | #define IMX95_PAD_GPIO_IO04__CAN4_TX 0x0020 0x0224 0x0000 0x03 0x00 |
| 73 | #define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0224 0x0000 0x04 0x00 |
| 74 | #define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0224 0x0580 0x05 0x01 |
| 75 | #define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0224 0x051C 0x16 0x01 |
| 76 | #define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x0020 0x0224 0x0478 0x07 0x00 |
| 77 | |
| 78 | #define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x0024 0x0228 0x0000 0x00 0x00 |
| 79 | #define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0228 0x0000 0x01 0x00 |
| 80 | #define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0024 0x0228 0x040C 0x02 0x01 |
| 81 | #define IMX95_PAD_GPIO_IO05__CAN4_RX 0x0024 0x0228 0x044C 0x03 0x01 |
| 82 | #define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0228 0x0000 0x04 0x00 |
| 83 | #define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0228 0x057C 0x05 0x01 |
| 84 | #define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0228 0x0518 0x16 0x01 |
| 85 | #define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x0024 0x0228 0x047C 0x07 0x00 |
| 86 | |
| 87 | #define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x0028 0x022C 0x0000 0x00 0x00 |
| 88 | #define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x022C 0x0000 0x01 0x00 |
| 89 | #define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0028 0x022C 0x0410 0x02 0x01 |
| 90 | #define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x022C 0x0000 0x04 0x00 |
| 91 | #define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x022C 0x0578 0x05 0x01 |
| 92 | #define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x022C 0x0524 0x16 0x00 |
| 93 | #define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x0028 0x022C 0x0480 0x07 0x00 |
| 94 | |
| 95 | #define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x002C 0x0230 0x0000 0x00 0x00 |
| 96 | #define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x0230 0x0000 0x01 0x00 |
| 97 | #define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x0230 0x0000 0x04 0x00 |
| 98 | #define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x0230 0x0000 0x05 0x00 |
| 99 | #define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x0230 0x0520 0x16 0x00 |
| 100 | #define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x002C 0x0230 0x0484 0x07 0x00 |
| 101 | |
| 102 | #define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x0030 0x0234 0x0000 0x00 0x00 |
| 103 | #define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0234 0x0000 0x01 0x00 |
| 104 | #define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0234 0x0000 0x04 0x00 |
| 105 | #define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0234 0x0588 0x05 0x01 |
| 106 | #define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0234 0x0524 0x16 0x01 |
| 107 | #define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x0030 0x0234 0x0488 0x07 0x00 |
| 108 | |
| 109 | #define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x0034 0x0238 0x0000 0x00 0x00 |
| 110 | #define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0238 0x0000 0x01 0x00 |
| 111 | #define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0238 0x0000 0x04 0x00 |
| 112 | #define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0238 0x0584 0x05 0x01 |
| 113 | #define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0238 0x0520 0x16 0x01 |
| 114 | #define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x0034 0x0238 0x048C 0x07 0x00 |
| 115 | |
| 116 | #define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x0038 0x023C 0x0000 0x00 0x00 |
| 117 | #define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x023C 0x0000 0x01 0x00 |
| 118 | #define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x023C 0x0000 0x04 0x00 |
| 119 | #define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x023C 0x0000 0x05 0x00 |
| 120 | #define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x023C 0x052C 0x16 0x00 |
| 121 | #define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x0038 0x023C 0x0490 0x07 0x00 |
| 122 | |
| 123 | #define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x003C 0x0240 0x0000 0x00 0x00 |
| 124 | #define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x0240 0x0000 0x01 0x00 |
| 125 | #define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x0240 0x0000 0x04 0x00 |
| 126 | #define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x0240 0x0000 0x05 0x00 |
| 127 | #define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x0240 0x0528 0x16 0x00 |
| 128 | #define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x003C 0x0240 0x0494 0x07 0x00 |
| 129 | |
| 130 | #define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x0040 0x0244 0x0000 0x00 0x00 |
| 131 | #define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0244 0x0000 0x01 0x00 |
| 132 | #define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0040 0x0244 0x0414 0x02 0x00 |
| 133 | #define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x0040 0x0244 0x0498 0x03 0x00 |
| 134 | #define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0244 0x0000 0x04 0x00 |
| 135 | #define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0244 0x0000 0x05 0x00 |
| 136 | #define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0244 0x052C 0x16 0x01 |
| 137 | #define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x0244 0x0590 0x07 0x00 |
| 138 | |
| 139 | #define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x0044 0x0248 0x0000 0x00 0x00 |
| 140 | #define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0248 0x0000 0x01 0x00 |
| 141 | #define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x0044 0x0248 0x0418 0x02 0x00 |
| 142 | #define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0248 0x0000 0x04 0x00 |
| 143 | #define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0248 0x0000 0x05 0x00 |
| 144 | #define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0248 0x0528 0x16 0x01 |
| 145 | #define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x0044 0x0248 0x049C 0x07 0x00 |
| 146 | |
| 147 | #define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x0048 0x024C 0x0000 0x00 0x00 |
| 148 | #define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x024C 0x055C 0x01 0x01 |
| 149 | #define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x024C 0x0000 0x04 0x00 |
| 150 | #define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x024C 0x0000 0x05 0x00 |
| 151 | #define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x024C 0x0568 0x06 0x01 |
| 152 | #define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x0048 0x024C 0x04A0 0x07 0x00 |
| 153 | |
| 154 | #define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x004C 0x0250 0x0000 0x00 0x00 |
| 155 | #define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x0250 0x0558 0x01 0x01 |
| 156 | #define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x0250 0x0000 0x04 0x00 |
| 157 | #define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x0250 0x0000 0x05 0x00 |
| 158 | #define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x0250 0x0564 0x06 0x01 |
| 159 | #define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x004C 0x0250 0x04A4 0x07 0x00 |
| 160 | |
| 161 | #define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x0050 0x0254 0x0000 0x00 0x00 |
| 162 | #define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0254 0x0000 0x01 0x00 |
| 163 | #define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0050 0x0254 0x0414 0x02 0x01 |
| 164 | #define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0254 0x0554 0x04 0x01 |
| 165 | #define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0254 0x0538 0x05 0x01 |
| 166 | #define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0254 0x0560 0x06 0x01 |
| 167 | #define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x0050 0x0254 0x04A8 0x07 0x00 |
| 168 | |
| 169 | #define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x0054 0x0258 0x0000 0x00 0x00 |
| 170 | #define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0258 0x0000 0x01 0x00 |
| 171 | #define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0258 0x0000 0x04 0x00 |
| 172 | #define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0258 0x0534 0x05 0x01 |
| 173 | #define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0258 0x0000 0x06 0x00 |
| 174 | #define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x0054 0x0258 0x04AC 0x07 0x00 |
| 175 | |
| 176 | #define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x0058 0x025C 0x0000 0x00 0x00 |
| 177 | #define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x025C 0x058C 0x01 0x00 |
| 178 | #define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x025C 0x0000 0x04 0x00 |
| 179 | #define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x025C 0x0530 0x05 0x01 |
| 180 | #define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x025C 0x0000 0x06 0x00 |
| 181 | #define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x0058 0x025C 0x04B0 0x07 0x00 |
| 182 | |
| 183 | #define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x005C 0x0260 0x0000 0x00 0x00 |
| 184 | #define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x0260 0x0590 0x01 0x01 |
| 185 | #define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x005C 0x0260 0x0418 0x02 0x01 |
| 186 | #define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x005C 0x0260 0x04B4 0x03 0x00 |
| 187 | #define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x0260 0x0000 0x04 0x00 |
| 188 | #define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x0260 0x0540 0x05 0x01 |
| 189 | #define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x0260 0x0000 0x06 0x00 |
| 190 | #define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x005C 0x0260 0x0000 0x07 0x00 |
| 191 | |
| 192 | #define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x0060 0x0264 0x0000 0x00 0x00 |
| 193 | #define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x0060 0x0264 0x0000 0x01 0x00 |
| 194 | #define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0060 0x0264 0x040C 0x02 0x02 |
| 195 | #define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0264 0x0000 0x04 0x00 |
| 196 | #define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0264 0x0544 0x05 0x01 |
| 197 | #define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0264 0x0000 0x06 0x00 |
| 198 | #define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x0060 0x0264 0x04B8 0x07 0x00 |
| 199 | |
| 200 | #define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x0064 0x0268 0x0000 0x00 0x00 |
| 201 | #define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x0064 0x0268 0x0000 0x01 0x00 |
| 202 | #define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0268 0x0000 0x02 0x00 |
| 203 | #define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x0064 0x0268 0x04BC 0x03 0x00 |
| 204 | #define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0268 0x0000 0x04 0x00 |
| 205 | #define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0268 0x053C 0x05 0x01 |
| 206 | #define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0268 0x0000 0x06 0x00 |
| 207 | #define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0268 0x058C 0x07 0x01 |
| 208 | |
| 209 | #define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x0068 0x026C 0x0000 0x00 0x00 |
| 210 | #define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x026C 0x05C8 0x01 0x00 |
| 211 | #define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x026C 0x0454 0x02 0x02 |
| 212 | #define IMX95_PAD_GPIO_IO22__CAN5_TX 0x0068 0x026C 0x0000 0x03 0x00 |
| 213 | #define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x026C 0x0000 0x04 0x00 |
| 214 | #define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x026C 0x0000 0x05 0x00 |
| 215 | #define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x026C 0x0514 0x16 0x01 |
| 216 | #define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x0068 0x026C 0x04C0 0x07 0x00 |
| 217 | |
| 218 | #define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x006C 0x0270 0x0000 0x00 0x00 |
| 219 | #define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x0270 0x05CC 0x01 0x00 |
| 220 | #define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x0270 0x0000 0x02 0x00 |
| 221 | #define IMX95_PAD_GPIO_IO23__CAN5_RX 0x006C 0x0270 0x0450 0x03 0x00 |
| 222 | #define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x0270 0x0000 0x04 0x00 |
| 223 | #define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x0270 0x0510 0x16 0x01 |
| 224 | #define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x006C 0x0270 0x04C4 0x07 0x00 |
| 225 | |
| 226 | #define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x0070 0x0274 0x0000 0x00 0x00 |
| 227 | #define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0274 0x05D0 0x01 0x00 |
| 228 | #define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0274 0x0000 0x04 0x00 |
| 229 | #define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0274 0x0000 0x05 0x00 |
| 230 | #define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0274 0x0000 0x06 0x00 |
| 231 | #define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x0070 0x0274 0x04C8 0x07 0x00 |
| 232 | |
| 233 | #define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x0074 0x0278 0x0000 0x00 0x00 |
| 234 | #define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0278 0x05D4 0x01 0x00 |
| 235 | #define IMX95_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0278 0x0000 0x02 0x00 |
| 236 | #define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0278 0x0000 0x04 0x00 |
| 237 | #define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0278 0x060C 0x05 0x01 |
| 238 | #define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0278 0x0000 0x06 0x00 |
| 239 | #define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x0074 0x0278 0x04CC 0x07 0x00 |
| 240 | |
| 241 | #define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x0078 0x027C 0x0000 0x00 0x00 |
| 242 | #define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x027C 0x05D8 0x01 0x00 |
| 243 | #define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0078 0x027C 0x0410 0x02 0x02 |
| 244 | #define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x0078 0x027C 0x0458 0x03 0x01 |
| 245 | #define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x027C 0x0000 0x04 0x00 |
| 246 | #define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x027C 0x0610 0x05 0x01 |
| 247 | #define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x027C 0x0000 0x06 0x00 |
| 248 | #define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x027C 0x0000 0x07 0x00 |
| 249 | |
| 250 | #define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x007C 0x0280 0x0000 0x00 0x00 |
| 251 | #define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x0280 0x05DC 0x01 0x00 |
| 252 | #define IMX95_PAD_GPIO_IO27__CAN2_RX 0x007C 0x0280 0x0444 0x02 0x02 |
| 253 | #define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x0280 0x0000 0x04 0x00 |
| 254 | #define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x0280 0x0614 0x05 0x01 |
| 255 | #define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x0280 0x0000 0x06 0x00 |
| 256 | #define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x007C 0x0280 0x045C 0x07 0x01 |
| 257 | |
| 258 | #define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x0080 0x0284 0x0000 0x00 0x00 |
| 259 | #define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0284 0x0504 0x11 0x01 |
| 260 | #define IMX95_PAD_GPIO_IO28__CAN3_TX 0x0080 0x0284 0x0000 0x02 0x00 |
| 261 | #define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x0080 0x0284 0x0000 0x07 0x00 |
| 262 | |
| 263 | #define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x0084 0x0288 0x0000 0x00 0x00 |
| 264 | #define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0288 0x0500 0x11 0x01 |
| 265 | #define IMX95_PAD_GPIO_IO29__CAN3_RX 0x0084 0x0288 0x0448 0x02 0x01 |
| 266 | #define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x0084 0x0288 0x0000 0x07 0x00 |
| 267 | |
| 268 | #define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x0088 0x028C 0x0000 0x00 0x00 |
| 269 | #define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x0088 0x028C 0x050C 0x11 0x01 |
| 270 | #define IMX95_PAD_GPIO_IO30__CAN5_TX 0x0088 0x028C 0x0000 0x02 0x00 |
| 271 | #define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x0088 0x028C 0x0460 0x07 0x01 |
| 272 | |
| 273 | #define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x008C 0x0290 0x0000 0x00 0x00 |
| 274 | #define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x008C 0x0290 0x0508 0x11 0x01 |
| 275 | #define IMX95_PAD_GPIO_IO31__CAN5_RX 0x008C 0x0290 0x0450 0x02 0x01 |
| 276 | #define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x008C 0x0290 0x0464 0x07 0x01 |
| 277 | |
| 278 | #define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x0090 0x0294 0x0000 0x00 0x00 |
| 279 | #define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x0294 0x0000 0x01 0x00 |
| 280 | #define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x0090 0x0294 0x0580 0x02 0x00 |
| 281 | #define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x0090 0x0294 0x0538 0x04 0x00 |
| 282 | |
| 283 | #define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x0094 0x0298 0x0000 0x00 0x00 |
| 284 | #define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x0094 0x0298 0x057C 0x02 0x00 |
| 285 | #define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x0094 0x0298 0x0534 0x04 0x00 |
| 286 | |
| 287 | #define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x0098 0x029C 0x0000 0x00 0x00 |
| 288 | #define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x0098 0x029C 0x0578 0x02 0x00 |
| 289 | #define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x0098 0x029C 0x0530 0x04 0x00 |
| 290 | |
| 291 | #define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x009C 0x02A0 0x0000 0x00 0x00 |
| 292 | #define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x009C 0x02A0 0x0000 0x01 0x00 |
| 293 | #define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x009C 0x02A0 0x0000 0x02 0x00 |
| 294 | #define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x009C 0x02A0 0x0540 0x04 0x00 |
| 295 | |
| 296 | #define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00A0 0x02A4 0x0544 0x04 0x00 |
| 297 | #define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00A0 0x02A4 0x0000 0x00 0x00 |
| 298 | #define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00A0 0x02A4 0x0588 0x02 0x00 |
| 299 | |
| 300 | #define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00A4 0x02A8 0x0000 0x00 0x00 |
| 301 | #define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00A4 0x02A8 0x0584 0x02 0x00 |
| 302 | #define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00A4 0x02A8 0x053C 0x04 0x00 |
| 303 | |
| 304 | #define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00A8 0x02AC 0x0000 0x00 0x00 |
| 305 | #define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00A8 0x02AC 0x0434 0x01 0x00 |
| 306 | #define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00A8 0x02AC 0x0458 0x04 0x00 |
| 307 | #define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00A8 0x02AC 0x0000 0x05 0x00 |
| 308 | |
| 309 | #define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00AC 0x02B0 0x0000 0x05 0x00 |
| 310 | #define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00AC 0x02B0 0x0000 0x00 0x00 |
| 311 | #define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00AC 0x02B0 0x0000 0x01 0x00 |
| 312 | #define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00AC 0x02B0 0x045C 0x04 0x00 |
| 313 | |
| 314 | #define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00B0 0x02B4 0x0000 0x00 0x00 |
| 315 | #define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00B0 0x02B4 0x0438 0x01 0x00 |
| 316 | #define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00B0 0x02B4 0x0000 0x02 0x00 |
| 317 | #define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00B0 0x02B4 0x0000 0x04 0x00 |
| 318 | #define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00B0 0x02B4 0x0000 0x05 0x00 |
| 319 | |
| 320 | #define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00B4 0x02B8 0x0000 0x00 0x00 |
| 321 | #define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00B4 0x02B8 0x0000 0x01 0x00 |
| 322 | #define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00B4 0x02B8 0x0448 0x02 0x00 |
| 323 | #define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00B4 0x02B8 0x0000 0x04 0x00 |
| 324 | #define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00B4 0x02B8 0x0000 0x05 0x00 |
| 325 | |
| 326 | #define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00B8 0x02BC 0x0424 0x00 0x00 |
| 327 | #define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00B8 0x02BC 0x0000 0x01 0x00 |
| 328 | #define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00B8 0x02BC 0x04F8 0x02 0x00 |
| 329 | #define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00B8 0x02BC 0x0000 0x03 0x00 |
| 330 | #define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00B8 0x02BC 0x0000 0x04 0x00 |
| 331 | #define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00B8 0x02BC 0x0000 0x05 0x00 |
| 332 | |
| 333 | #define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00BC 0x02C0 0x0428 0x00 0x00 |
| 334 | #define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00BC 0x02C0 0x0000 0x01 0x00 |
| 335 | #define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00BC 0x02C0 0x04FC 0x02 0x00 |
| 336 | #define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00BC 0x02C0 0x0000 0x03 0x00 |
| 337 | #define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00BC 0x02C0 0x0000 0x04 0x00 |
| 338 | #define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00BC 0x02C0 0x0000 0x05 0x00 |
| 339 | |
| 340 | #define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00C0 0x02C4 0x0000 0x00 0x00 |
| 341 | #define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00C0 0x02C4 0x0000 0x02 0x00 |
| 342 | #define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00C0 0x02C4 0x0000 0x03 0x00 |
| 343 | #define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00C0 0x02C4 0x0000 0x04 0x00 |
| 344 | #define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00C0 0x02C4 0x0000 0x05 0x00 |
| 345 | |
| 346 | #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00C4 0x02C8 0x0000 0x00 0x00 |
| 347 | #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00C4 0x02C8 0x0000 0x01 0x00 |
| 348 | #define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00C4 0x02C8 0x0444 0x02 0x01 |
| 349 | #define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00C4 0x02C8 0x0000 0x03 0x00 |
| 350 | #define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00C4 0x02C8 0x0000 0x04 0x00 |
| 351 | #define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00C4 0x02C8 0x0000 0x05 0x00 |
| 352 | |
| 353 | #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00C8 0x02CC 0x0000 0x00 0x00 |
| 354 | #define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00C8 0x02CC 0x0000 0x01 0x00 |
| 355 | #define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00C8 0x02CC 0x0000 0x02 0x00 |
| 356 | #define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00C8 0x02CC 0x0000 0x03 0x00 |
| 357 | #define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00C8 0x02CC 0x0000 0x04 0x00 |
| 358 | #define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00C8 0x02CC 0x0000 0x05 0x00 |
| 359 | #define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00C8 0x02CC 0x0000 0x06 0x00 |
| 360 | #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00C8 0x02CC 0x0000 0x07 0x00 |
| 361 | |
| 362 | #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00CC 0x02D0 0x0000 0x00 0x00 |
| 363 | #define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00CC 0x02D0 0x055C 0x01 0x00 |
| 364 | #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00CC 0x02D0 0x0000 0x02 0x00 |
| 365 | #define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00CC 0x02D0 0x0000 0x04 0x00 |
| 366 | #define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00CC 0x02D0 0x0000 0x05 0x00 |
| 367 | |
| 368 | #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00D0 0x02D4 0x0000 0x00 0x00 |
| 369 | #define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00D0 0x02D4 0x0000 0x01 0x00 |
| 370 | #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00D0 0x02D4 0x0000 0x02 0x00 |
| 371 | #define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00D0 0x02D4 0x0000 0x04 0x00 |
| 372 | #define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00D0 0x02D4 0x0000 0x05 0x00 |
| 373 | |
| 374 | #define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00D4 0x02D8 0x0000 0x00 0x00 |
| 375 | #define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00D4 0x02D8 0x0000 0x01 0x00 |
| 376 | #define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00D4 0x02D8 0x0000 0x04 0x00 |
| 377 | #define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00D4 0x02D8 0x0000 0x05 0x00 |
| 378 | |
| 379 | #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00D8 0x02DC 0x0000 0x00 0x00 |
| 380 | #define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00D8 0x02DC 0x0000 0x01 0x00 |
| 381 | #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00D8 0x02DC 0x0000 0x02 0x00 |
| 382 | #define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00D8 0x02DC 0x0000 0x03 0x00 |
| 383 | #define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00D8 0x02DC 0x0000 0x04 0x00 |
| 384 | #define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00D8 0x02DC 0x0000 0x05 0x00 |
| 385 | |
| 386 | #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00DC 0x02E0 0x0000 0x00 0x00 |
| 387 | #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00DC 0x02E0 0x042C 0x01 0x00 |
| 388 | #define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00DC 0x02E0 0x0000 0x04 0x00 |
| 389 | #define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00DC 0x02E0 0x0000 0x05 0x00 |
| 390 | |
| 391 | #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00E0 0x02E4 0x0000 0x00 0x00 |
| 392 | #define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00E0 0x02E4 0x0558 0x01 0x00 |
| 393 | #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00E0 0x02E4 0x0000 0x02 0x00 |
| 394 | #define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00E0 0x02E4 0x0000 0x04 0x00 |
| 395 | #define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00E0 0x02E4 0x0000 0x05 0x00 |
| 396 | |
| 397 | #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00E4 0x02E8 0x0000 0x00 0x00 |
| 398 | #define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00E4 0x02E8 0x0554 0x01 0x00 |
| 399 | #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00E4 0x02E8 0x0000 0x02 0x00 |
| 400 | #define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00E4 0x02E8 0x0548 0x03 0x00 |
| 401 | #define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00E4 0x02E8 0x0000 0x04 0x00 |
| 402 | #define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00E4 0x02E8 0x0000 0x05 0x00 |
| 403 | |
| 404 | #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00E8 0x02EC 0x0000 0x00 0x00 |
| 405 | #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00E8 0x02EC 0x042C 0x02 0x01 |
| 406 | #define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00E8 0x02EC 0x054C 0x03 0x00 |
| 407 | #define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00E8 0x02EC 0x0000 0x04 0x00 |
| 408 | #define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00E8 0x02EC 0x0000 0x05 0x00 |
| 409 | |
| 410 | #define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00EC 0x02F0 0x0000 0x00 0x00 |
| 411 | #define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00EC 0x02F0 0x0550 0x03 0x00 |
| 412 | #define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00EC 0x02F0 0x0000 0x04 0x00 |
| 413 | #define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00EC 0x02F0 0x0000 0x05 0x00 |
| 414 | |
| 415 | #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00F0 0x02F4 0x0424 0x00 0x01 |
| 416 | #define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00F0 0x02F4 0x0000 0x01 0x00 |
| 417 | #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00F0 0x02F4 0x0000 0x02 0x00 |
| 418 | #define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00F0 0x02F4 0x0000 0x04 0x00 |
| 419 | #define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00F0 0x02F4 0x0000 0x05 0x00 |
| 420 | |
| 421 | #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00F4 0x02F8 0x0428 0x00 0x01 |
| 422 | #define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00F4 0x02F8 0x0000 0x01 0x00 |
| 423 | #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00F4 0x02F8 0x0000 0x02 0x00 |
| 424 | #define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00F4 0x02F8 0x0000 0x04 0x00 |
| 425 | #define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00F4 0x02F8 0x0000 0x05 0x00 |
| 426 | |
| 427 | #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00F8 0x02FC 0x0000 0x02 0x00 |
| 428 | #define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00F8 0x02FC 0x0000 0x04 0x00 |
| 429 | #define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00F8 0x02FC 0x0000 0x05 0x00 |
| 430 | #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00F8 0x02FC 0x0000 0x00 0x00 |
| 431 | |
| 432 | #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00FC 0x0300 0x0000 0x00 0x00 |
| 433 | #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00FC 0x0300 0x0000 0x01 0x00 |
| 434 | #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00FC 0x0300 0x0000 0x02 0x00 |
| 435 | #define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00FC 0x0300 0x05A4 0x03 0x00 |
| 436 | #define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00FC 0x0300 0x0000 0x04 0x00 |
| 437 | #define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00FC 0x0300 0x0000 0x05 0x00 |
| 438 | |
| 439 | #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x0100 0x0304 0x0000 0x00 0x00 |
| 440 | #define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x0100 0x0304 0x0000 0x01 0x00 |
| 441 | #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x0100 0x0304 0x0000 0x02 0x00 |
| 442 | #define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x0100 0x0304 0x05A0 0x03 0x00 |
| 443 | #define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x0100 0x0304 0x0000 0x04 0x00 |
| 444 | #define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x0100 0x0304 0x0000 0x05 0x00 |
| 445 | #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x0100 0x0304 0x0000 0x06 0x00 |
| 446 | |
| 447 | #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0104 0x0308 0x0000 0x00 0x00 |
| 448 | #define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x0104 0x0308 0x0568 0x01 0x00 |
| 449 | #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x0104 0x0308 0x0000 0x02 0x00 |
| 450 | #define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x0104 0x0308 0x0000 0x03 0x00 |
| 451 | #define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x0104 0x0308 0x0000 0x04 0x00 |
| 452 | #define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x0104 0x0308 0x0000 0x05 0x00 |
| 453 | #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0104 0x0308 0x0000 0x06 0x00 |
| 454 | |
| 455 | #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0108 0x030C 0x0000 0x00 0x00 |
| 456 | #define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x0108 0x030C 0x0000 0x01 0x00 |
| 457 | #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0108 0x030C 0x0000 0x02 0x00 |
| 458 | #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0108 0x030C 0x0000 0x03 0x00 |
| 459 | #define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x0108 0x030C 0x0000 0x04 0x00 |
| 460 | #define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x0108 0x030C 0x0000 0x05 0x00 |
| 461 | |
| 462 | #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x010C 0x0310 0x0000 0x00 0x00 |
| 463 | #define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x010C 0x0310 0x0000 0x01 0x00 |
| 464 | #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x010C 0x0310 0x0000 0x02 0x00 |
| 465 | #define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x010C 0x0310 0x0000 0x04 0x00 |
| 466 | #define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x010C 0x0310 0x0000 0x05 0x00 |
| 467 | |
| 468 | #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x0110 0x0314 0x0000 0x00 0x00 |
| 469 | #define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x0110 0x0314 0x0000 0x01 0x00 |
| 470 | #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x0110 0x0314 0x0000 0x02 0x00 |
| 471 | #define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x0110 0x0314 0x0000 0x04 0x00 |
| 472 | #define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x0110 0x0314 0x0000 0x05 0x00 |
| 473 | #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x0110 0x0314 0x0000 0x06 0x00 |
| 474 | |
| 475 | #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0114 0x0318 0x0000 0x00 0x00 |
| 476 | #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0114 0x0318 0x0430 0x01 0x00 |
| 477 | #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x0114 0x0318 0x0000 0x02 0x00 |
| 478 | #define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x0114 0x0318 0x059C 0x03 0x00 |
| 479 | #define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x0114 0x0318 0x0000 0x04 0x00 |
| 480 | #define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x0114 0x0318 0x0000 0x05 0x00 |
| 481 | |
| 482 | #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0118 0x031C 0x0000 0x00 0x00 |
| 483 | #define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x0118 0x031C 0x0564 0x01 0x00 |
| 484 | #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x0118 0x031C 0x0000 0x02 0x00 |
| 485 | #define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x0118 0x031C 0x0594 0x03 0x00 |
| 486 | #define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x0118 0x031C 0x0000 0x04 0x00 |
| 487 | #define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x0118 0x031C 0x0000 0x05 0x00 |
| 488 | #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0118 0x031C 0x0000 0x06 0x00 |
| 489 | |
| 490 | #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x011C 0x0320 0x0000 0x00 0x00 |
| 491 | #define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x011C 0x0320 0x0454 0x01 0x00 |
| 492 | #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x011C 0x0320 0x0000 0x02 0x00 |
| 493 | #define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x011C 0x0320 0x0598 0x03 0x00 |
| 494 | #define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x011C 0x0320 0x0000 0x04 0x00 |
| 495 | #define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x011C 0x0320 0x0000 0x05 0x00 |
| 496 | #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x011C 0x0320 0x0000 0x06 0x00 |
| 497 | |
| 498 | #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x0120 0x0324 0x0000 0x00 0x00 |
| 499 | #define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x0120 0x0324 0x0560 0x01 0x00 |
| 500 | #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x0120 0x0324 0x0000 0x02 0x00 |
| 501 | #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x0120 0x0324 0x0000 0x03 0x00 |
| 502 | #define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x0120 0x0324 0x0000 0x04 0x00 |
| 503 | #define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x0120 0x0324 0x0000 0x05 0x00 |
| 504 | #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0120 0x0324 0x0430 0x06 0x01 |
| 505 | |
| 506 | #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0124 0x0328 0x0000 0x00 0x00 |
| 507 | #define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x0124 0x0328 0x0000 0x01 0x00 |
| 508 | #define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x0124 0x0328 0x0454 0x02 0x01 |
| 509 | #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0124 0x0328 0x0000 0x03 0x00 |
| 510 | #define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x0124 0x0328 0x0000 0x04 0x00 |
| 511 | #define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x0124 0x0328 0x0000 0x05 0x00 |
| 512 | |
| 513 | #define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x0128 0x032C 0x0488 0x04 0x01 |
| 514 | #define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x0128 0x032C 0x0000 0x05 0x00 |
| 515 | #define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x0128 0x032C 0x0000 0x00 0x00 |
| 516 | |
| 517 | #define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x012C 0x0330 0x0000 0x00 0x00 |
| 518 | #define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x012C 0x0330 0x048C 0x04 0x01 |
| 519 | #define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x012C 0x0330 0x0000 0x05 0x00 |
| 520 | |
| 521 | #define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x0130 0x0334 0x0000 0x00 0x00 |
| 522 | #define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x0130 0x0334 0x0490 0x04 0x01 |
| 523 | #define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x0130 0x0334 0x0000 0x05 0x00 |
| 524 | |
| 525 | #define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x0134 0x0338 0x0000 0x00 0x00 |
| 526 | #define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x0134 0x0338 0x0494 0x04 0x01 |
| 527 | #define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x0134 0x0338 0x0000 0x05 0x00 |
| 528 | |
| 529 | #define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x0138 0x033C 0x0000 0x00 0x00 |
| 530 | #define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x0138 0x033C 0x0498 0x04 0x01 |
| 531 | #define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x0138 0x033C 0x0000 0x05 0x00 |
| 532 | #define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0138 0x033C 0x0000 0x06 0x00 |
| 533 | |
| 534 | #define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x013C 0x0340 0x0000 0x00 0x00 |
| 535 | #define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x013C 0x0340 0x0000 0x01 0x00 |
| 536 | #define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x013C 0x0340 0x049C 0x04 0x01 |
| 537 | #define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x013C 0x0340 0x0000 0x05 0x00 |
| 538 | |
| 539 | #define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x0140 0x0344 0x0000 0x00 0x00 |
| 540 | #define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0140 0x0344 0x04E4 0x01 0x00 |
| 541 | #define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x0140 0x0344 0x04A0 0x04 0x01 |
| 542 | #define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x0140 0x0344 0x0000 0x05 0x00 |
| 543 | #define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x0140 0x0344 0x05FC 0x06 0x00 |
| 544 | |
| 545 | #define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x0144 0x0348 0x0000 0x00 0x00 |
| 546 | #define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0144 0x0348 0x04E8 0x01 0x00 |
| 547 | #define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x0144 0x0348 0x0000 0x02 0x00 |
| 548 | #define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x0144 0x0348 0x04A4 0x04 0x01 |
| 549 | #define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x0144 0x0348 0x0000 0x05 0x00 |
| 550 | #define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x0144 0x0348 0x0600 0x06 0x00 |
| 551 | |
| 552 | #define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x0148 0x034C 0x0000 0x00 0x00 |
| 553 | #define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0148 0x034C 0x04EC 0x01 0x00 |
| 554 | #define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x0148 0x034C 0x0000 0x02 0x00 |
| 555 | #define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x0148 0x034C 0x04A8 0x04 0x01 |
| 556 | #define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x0148 0x034C 0x0000 0x05 0x00 |
| 557 | #define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x0148 0x034C 0x0604 0x06 0x00 |
| 558 | |
| 559 | #define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x014C 0x0350 0x0000 0x00 0x00 |
| 560 | #define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x014C 0x0350 0x04F0 0x01 0x00 |
| 561 | #define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x014C 0x0350 0x0000 0x02 0x00 |
| 562 | #define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x014C 0x0350 0x04AC 0x04 0x01 |
| 563 | #define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x014C 0x0350 0x0000 0x05 0x00 |
| 564 | #define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x014C 0x0350 0x0608 0x06 0x00 |
| 565 | |
| 566 | #define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x0150 0x0354 0x0000 0x00 0x00 |
| 567 | #define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0150 0x0354 0x04D0 0x01 0x00 |
| 568 | #define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x0150 0x0354 0x04B0 0x04 0x01 |
| 569 | #define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x0150 0x0354 0x0000 0x05 0x00 |
| 570 | #define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x0150 0x0354 0x05E4 0x06 0x00 |
| 571 | |
| 572 | #define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0154 0x0358 0x0000 0x00 0x00 |
| 573 | #define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x0154 0x0358 0x0000 0x01 0x00 |
| 574 | #define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0154 0x0358 0x0550 0x02 0x01 |
| 575 | #define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x0154 0x0358 0x04B4 0x04 0x01 |
| 576 | #define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x0154 0x0358 0x0000 0x05 0x00 |
| 577 | #define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0154 0x0358 0x0420 0x06 0x01 |
| 578 | |
| 579 | #define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x0158 0x035C 0x05C8 0x00 0x01 |
| 580 | #define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0158 0x035C 0x04F4 0x01 0x00 |
| 581 | #define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x0158 0x035C 0x0000 0x02 0x00 |
| 582 | #define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x0158 0x035C 0x05AC 0x03 0x00 |
| 583 | #define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x0158 0x035C 0x04B8 0x04 0x01 |
| 584 | #define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x0158 0x035C 0x0000 0x05 0x00 |
| 585 | #define IMX95_PAD_SD3_CLK__XSPI_CLK 0x0158 0x035C 0x05E8 0x06 0x00 |
| 586 | |
| 587 | #define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x015C 0x0360 0x05CC 0x00 0x01 |
| 588 | #define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x015C 0x0360 0x0000 0x01 0x00 |
| 589 | #define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x015C 0x0360 0x0000 0x02 0x00 |
| 590 | #define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x015C 0x0360 0x05BC 0x03 0x00 |
| 591 | #define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x015C 0x0360 0x04BC 0x04 0x01 |
| 592 | #define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x015C 0x0360 0x0000 0x05 0x00 |
| 593 | #define IMX95_PAD_SD3_CMD__XSPI_CS 0x015C 0x0360 0x05E0 0x06 0x00 |
| 594 | |
| 595 | #define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x0160 0x0364 0x05D0 0x00 0x01 |
| 596 | #define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x0160 0x0364 0x04D4 0x01 0x00 |
| 597 | #define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x0160 0x0364 0x0000 0x02 0x00 |
| 598 | #define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x0160 0x0364 0x05A8 0x03 0x00 |
| 599 | #define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x0160 0x0364 0x04C0 0x04 0x01 |
| 600 | #define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x0160 0x0364 0x0000 0x05 0x00 |
| 601 | #define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x0160 0x0364 0x05EC 0x06 0x00 |
| 602 | |
| 603 | #define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x0164 0x0368 0x05D4 0x00 0x01 |
| 604 | #define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x0164 0x0368 0x04D8 0x01 0x00 |
| 605 | #define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x0164 0x0368 0x05B0 0x02 0x00 |
| 606 | #define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x0164 0x0368 0x0000 0x03 0x00 |
| 607 | #define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x0164 0x0368 0x04C4 0x04 0x01 |
| 608 | #define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x0164 0x0368 0x0000 0x05 0x00 |
| 609 | #define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x0164 0x0368 0x05F0 0x06 0x00 |
| 610 | |
| 611 | #define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x0168 0x036C 0x05D8 0x00 0x01 |
| 612 | #define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x0168 0x036C 0x04DC 0x01 0x00 |
| 613 | #define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x0168 0x036C 0x05B4 0x02 0x00 |
| 614 | #define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x0168 0x036C 0x05C4 0x03 0x00 |
| 615 | #define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x0168 0x036C 0x04C8 0x04 0x01 |
| 616 | #define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x0168 0x036C 0x0000 0x05 0x00 |
| 617 | #define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x0168 0x036C 0x05F4 0x06 0x00 |
| 618 | |
| 619 | #define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x016C 0x0370 0x05DC 0x00 0x01 |
| 620 | #define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x016C 0x0370 0x04E0 0x01 0x00 |
| 621 | #define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x016C 0x0370 0x05B8 0x02 0x00 |
| 622 | #define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x016C 0x0370 0x05C0 0x03 0x00 |
| 623 | #define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x016C 0x0370 0x04CC 0x04 0x01 |
| 624 | #define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x016C 0x0370 0x0000 0x05 0x00 |
| 625 | #define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x016C 0x0370 0x05F8 0x06 0x00 |
| 626 | |
| 627 | #define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x0170 0x0374 0x04D4 0x00 0x01 |
| 628 | #define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x0170 0x0374 0x0000 0x01 0x00 |
| 629 | #define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x0170 0x0374 0x05A0 0x02 0x01 |
| 630 | #define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x0170 0x0374 0x0000 0x03 0x00 |
| 631 | #define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x0170 0x0374 0x05EC 0x04 0x01 |
| 632 | #define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x0170 0x0374 0x0000 0x05 0x00 |
| 633 | |
| 634 | #define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x0174 0x0378 0x04D8 0x00 0x01 |
| 635 | #define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x0174 0x0378 0x0000 0x01 0x00 |
| 636 | #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x0174 0x0378 0x05A4 0x02 0x01 |
| 637 | #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x0174 0x0378 0x0000 0x03 0x00 |
| 638 | #define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x0174 0x0378 0x05F0 0x04 0x01 |
| 639 | #define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x0174 0x0378 0x0000 0x05 0x00 |
| 640 | |
| 641 | #define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x0178 0x037C 0x04DC 0x00 0x01 |
| 642 | #define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x0178 0x037C 0x0000 0x01 0x00 |
| 643 | #define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x0178 0x037C 0x0000 0x02 0x00 |
| 644 | #define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x0178 0x037C 0x05F4 0x04 0x01 |
| 645 | #define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x0178 0x037C 0x0000 0x05 0x00 |
| 646 | |
| 647 | #define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x017C 0x0380 0x04E0 0x00 0x01 |
| 648 | #define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x017C 0x0380 0x0000 0x01 0x00 |
| 649 | #define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x017C 0x0380 0x0598 0x02 0x01 |
| 650 | #define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x017C 0x0380 0x05F8 0x04 0x01 |
| 651 | #define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x017C 0x0380 0x0000 0x05 0x00 |
| 652 | |
| 653 | #define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0180 0x0384 0x04E4 0x00 0x01 |
| 654 | #define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x0180 0x0384 0x0000 0x01 0x00 |
| 655 | #define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x0180 0x0384 0x05B0 0x02 0x01 |
| 656 | #define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x0180 0x0384 0x05FC 0x04 0x01 |
| 657 | #define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x0180 0x0384 0x0000 0x05 0x00 |
| 658 | |
| 659 | #define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0184 0x0388 0x04E8 0x00 0x01 |
| 660 | #define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x0184 0x0388 0x05C4 0x01 0x01 |
| 661 | #define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x0184 0x0388 0x05B4 0x02 0x01 |
| 662 | #define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0184 0x0388 0x043C 0x03 0x00 |
| 663 | #define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x0184 0x0388 0x0600 0x04 0x01 |
| 664 | #define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x0184 0x0388 0x0000 0x05 0x00 |
| 665 | |
| 666 | #define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0188 0x038C 0x04EC 0x00 0x01 |
| 667 | #define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x0188 0x038C 0x05C0 0x01 0x01 |
| 668 | #define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x0188 0x038C 0x05B8 0x02 0x01 |
| 669 | #define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x0188 0x038C 0x0440 0x03 0x00 |
| 670 | #define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x0188 0x038C 0x0604 0x04 0x01 |
| 671 | #define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x0188 0x038C 0x0000 0x05 0x00 |
| 672 | |
| 673 | #define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x018C 0x0390 0x04F0 0x00 0x01 |
| 674 | #define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x018C 0x0390 0x05AC 0x01 0x01 |
| 675 | #define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x018C 0x0390 0x0000 0x02 0x00 |
| 676 | #define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x018C 0x0390 0x0608 0x04 0x01 |
| 677 | #define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x018C 0x0390 0x0000 0x05 0x00 |
| 678 | |
| 679 | #define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x0190 0x0394 0x04D0 0x00 0x01 |
| 680 | #define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x0190 0x0394 0x05BC 0x01 0x01 |
| 681 | #define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x0190 0x0394 0x0000 0x02 0x00 |
| 682 | #define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0190 0x0394 0x043C 0x03 0x01 |
| 683 | #define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x0190 0x0394 0x05E4 0x04 0x01 |
| 684 | #define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x0190 0x0394 0x0000 0x05 0x00 |
| 685 | |
| 686 | #define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x0194 0x0398 0x04F4 0x00 0x01 |
| 687 | #define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x0194 0x0398 0x0000 0x01 0x00 |
| 688 | #define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x0194 0x0398 0x059C 0x02 0x01 |
| 689 | #define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x0194 0x0398 0x0000 0x03 0x00 |
| 690 | #define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x0194 0x0398 0x05E8 0x04 0x01 |
| 691 | #define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x0194 0x0398 0x0000 0x05 0x00 |
| 692 | |
| 693 | #define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x0198 0x039C 0x0000 0x00 0x00 |
| 694 | #define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x0198 0x039C 0x0000 0x01 0x00 |
| 695 | #define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0198 0x039C 0x0594 0x02 0x01 |
| 696 | #define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x0198 0x039C 0x0000 0x03 0x00 |
| 697 | #define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x0198 0x039C 0x05E0 0x04 0x01 |
| 698 | #define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x0198 0x039C 0x0000 0x05 0x00 |
| 699 | |
| 700 | #define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x019C 0x03A0 0x0000 0x00 0x00 |
| 701 | #define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x019C 0x03A0 0x05A8 0x01 0x01 |
| 702 | #define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x019C 0x03A0 0x0000 0x02 0x00 |
| 703 | #define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x019C 0x03A0 0x0440 0x03 0x01 |
| 704 | #define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x019C 0x03A0 0x0000 0x05 0x00 |
| 705 | |
| 706 | #define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01A0 0x03A4 0x0000 0x00 0x00 |
| 707 | #define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01A0 0x03A4 0x0434 0x01 0x01 |
| 708 | #define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01A0 0x03A4 0x04F8 0x02 0x01 |
| 709 | #define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01A0 0x03A4 0x0468 0x04 0x01 |
| 710 | #define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01A0 0x03A4 0x0000 0x05 0x00 |
| 711 | |
| 712 | #define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01A4 0x03A8 0x0000 0x00 0x00 |
| 713 | #define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01A4 0x03A8 0x0000 0x01 0x00 |
| 714 | #define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01A4 0x03A8 0x04FC 0x02 0x01 |
| 715 | #define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01A4 0x03A8 0x046C 0x04 0x01 |
| 716 | #define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01A4 0x03A8 0x0000 0x05 0x00 |
| 717 | #define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01A4 0x03A8 0x0000 0x06 0x00 |
| 718 | |
| 719 | #define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01A8 0x03AC 0x0000 0x00 0x00 |
| 720 | #define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01A8 0x03AC 0x0438 0x01 0x01 |
| 721 | #define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01A8 0x03AC 0x0000 0x02 0x00 |
| 722 | #define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01A8 0x03AC 0x0000 0x03 0x00 |
| 723 | #define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01A8 0x03AC 0x0470 0x04 0x01 |
| 724 | #define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01A8 0x03AC 0x0000 0x05 0x00 |
| 725 | #define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01A8 0x03AC 0x0000 0x06 0x00 |
| 726 | |
| 727 | #define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01AC 0x03B0 0x0000 0x00 0x00 |
| 728 | #define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01AC 0x03B0 0x0000 0x01 0x00 |
| 729 | #define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01AC 0x03B0 0x0000 0x02 0x00 |
| 730 | #define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01AC 0x03B0 0x0474 0x04 0x01 |
| 731 | #define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01AC 0x03B0 0x0000 0x05 0x00 |
| 732 | #define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01AC 0x03B0 0x0000 0x06 0x00 |
| 733 | |
| 734 | #define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01B0 0x03B4 0x0000 0x00 0x00 |
| 735 | #define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01B0 0x03B4 0x0000 0x01 0x00 |
| 736 | #define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01B0 0x03B4 0x0444 0x02 0x03 |
| 737 | #define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01B0 0x03B4 0x0478 0x04 0x01 |
| 738 | #define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01B0 0x03B4 0x0000 0x05 0x00 |
| 739 | |
| 740 | #define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01B4 0x03B8 0x0000 0x00 0x00 |
| 741 | #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01B4 0x03B8 0x0000 0x01 0x00 |
| 742 | #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01B4 0x03B8 0x0000 0x02 0x00 |
| 743 | #define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01B4 0x03B8 0x047C 0x04 0x01 |
| 744 | #define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01B4 0x03B8 0x0000 0x05 0x00 |
| 745 | |
| 746 | #define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01B8 0x03BC 0x0000 0x00 0x00 |
| 747 | #define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01B8 0x03BC 0x0548 0x01 0x01 |
| 748 | #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01B8 0x03BC 0x0000 0x02 0x00 |
| 749 | #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01B8 0x03BC 0x0000 0x03 0x00 |
| 750 | #define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01B8 0x03BC 0x0480 0x04 0x01 |
| 751 | #define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01B8 0x03BC 0x0000 0x05 0x00 |
| 752 | |
| 753 | #define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01BC 0x03C0 0x0000 0x00 0x00 |
| 754 | #define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01BC 0x03C0 0x054C 0x01 0x01 |
| 755 | #define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01BC 0x03C0 0x0000 0x03 0x00 |
| 756 | #define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01BC 0x03C0 0x0484 0x04 0x01 |
| 757 | #define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01BC 0x03C0 0x0000 0x05 0x00 |
| 758 | |
| 759 | #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01C0 0x03C4 0x0000 0x00 0x00 |
| 760 | #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01C0 0x03C4 0x0000 0x01 0x00 |
| 761 | #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01C0 0x03C4 0x0000 0x02 0x00 |
| 762 | #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01C0 0x03C4 0x0000 0x03 0x00 |
| 763 | #define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01C0 0x03C4 0x0000 0x04 0x00 |
| 764 | #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01C0 0x03C4 0x0000 0x05 0x00 |
| 765 | |
| 766 | #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01C4 0x03C8 0x0000 0x00 0x00 |
| 767 | #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01C4 0x03C8 0x0000 0x01 0x00 |
| 768 | #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01C4 0x03C8 0x0000 0x02 0x00 |
| 769 | #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01C4 0x03C8 0x0000 0x03 0x00 |
| 770 | #define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01C4 0x03C8 0x0000 0x04 0x00 |
| 771 | #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01C4 0x03C8 0x0000 0x05 0x00 |
| 772 | |
| 773 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01C8 0x03CC 0x0000 0x00 0x00 |
| 774 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01C8 0x03CC 0x0000 0x01 0x00 |
| 775 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01C8 0x03CC 0x0000 0x02 0x00 |
| 776 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01C8 0x03CC 0x0000 0x03 0x00 |
| 777 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01C8 0x03CC 0x0000 0x04 0x00 |
| 778 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01C8 0x03CC 0x0000 0x05 0x00 |
| 779 | #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01C8 0x03CC 0x0000 0x06 0x00 |
| 780 | |
| 781 | #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01CC 0x03D0 0x0000 0x00 0x00 |
| 782 | #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01CC 0x03D0 0x0000 0x02 0x00 |
| 783 | #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01CC 0x03D0 0x0000 0x03 0x00 |
| 784 | #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01CC 0x03D0 0x0000 0x04 0x00 |
| 785 | #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01CC 0x03D0 0x0000 0x05 0x00 |
| 786 | |
| 787 | #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01D0 0x03D4 0x0000 0x00 0x00 |
| 788 | #define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01D0 0x03D4 0x0000 0x01 0x00 |
| 789 | #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01D0 0x03D4 0x0000 0x02 0x00 |
| 790 | #define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01D0 0x03D4 0x0000 0x03 0x00 |
| 791 | #define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01D0 0x03D4 0x0000 0x05 0x00 |
| 792 | |
| 793 | #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01D4 0x03D8 0x0000 0x00 0x00 |
| 794 | #define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01D4 0x03D8 0x0000 0x01 0x00 |
| 795 | #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01D4 0x03D8 0x0000 0x02 0x00 |
| 796 | #define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01D4 0x03D8 0x0000 0x03 0x00 |
| 797 | #define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01D4 0x03D8 0x0000 0x05 0x00 |
| 798 | |
| 799 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01D8 0x03DC 0x0000 0x00 0x00 |
| 800 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01D8 0x03DC 0x0000 0x01 0x00 |
| 801 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01D8 0x03DC 0x0000 0x02 0x00 |
| 802 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01D8 0x03DC 0x0000 0x03 0x00 |
| 803 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01D8 0x03DC 0x041C 0x04 0x00 |
| 804 | #define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01D8 0x03DC 0x0000 0x05 0x00 |
| 805 | |
| 806 | #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01DC 0x03E0 0x0000 0x00 0x00 |
| 807 | #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01DC 0x03E0 0x0000 0x01 0x00 |
| 808 | #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01DC 0x03E0 0x0000 0x02 0x00 |
| 809 | #define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01DC 0x03E0 0x0000 0x03 0x00 |
| 810 | #define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01DC 0x03E0 0x0000 0x05 0x00 |
| 811 | |
| 812 | #define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01E0 0x03E4 0x0000 0x00 0x00 |
| 813 | #define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01E0 0x03E4 0x0000 0x01 0x00 |
| 814 | #define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01E0 0x03E4 0x0000 0x04 0x00 |
| 815 | #define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01E0 0x03E4 0x0000 0x05 0x00 |
| 816 | #define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01E0 0x03E4 0x0000 0x06 0x00 |
| 817 | |
| 818 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01E4 0x03E8 0x040C 0x00 0x00 |
| 819 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01E4 0x03E8 0x0000 0x01 0x00 |
| 820 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01E4 0x03E8 0x0000 0x02 0x00 |
| 821 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01E4 0x03E8 0x0000 0x03 0x00 |
| 822 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01E4 0x03E8 0x0000 0x04 0x00 |
| 823 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01E4 0x03E8 0x0000 0x05 0x00 |
| 824 | #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01E4 0x03E8 0x0408 0x06 0x00 |
| 825 | |
| 826 | #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01E8 0x03EC 0x0410 0x00 0x00 |
| 827 | #define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01E8 0x03EC 0x0000 0x01 0x00 |
| 828 | #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01E8 0x03EC 0x0000 0x02 0x00 |
| 829 | #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01E8 0x03EC 0x0000 0x03 0x00 |
| 830 | #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01E8 0x03EC 0x0000 0x04 0x00 |
| 831 | #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01E8 0x03EC 0x0000 0x05 0x00 |
| 832 | #define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01E8 0x03EC 0x0420 0x06 0x00 |
| 833 | |
| 834 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01EC 0x03F0 0x0000 0x00 0x00 |
| 835 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01EC 0x03F0 0x0000 0x01 0x00 |
| 836 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01EC 0x03F0 0x0000 0x02 0x00 |
| 837 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01EC 0x03F0 0x0000 0x03 0x00 |
| 838 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01EC 0x03F0 0x0000 0x04 0x00 |
| 839 | #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01EC 0x03F0 0x0000 0x05 0x00 |
| 840 | |
| 841 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01F0 0x03F4 0x0000 0x00 0x00 |
| 842 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01F0 0x03F4 0x0000 0x01 0x00 |
| 843 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01F0 0x03F4 0x0000 0x02 0x00 |
| 844 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01F0 0x03F4 0x0000 0x03 0x00 |
| 845 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01F0 0x03F4 0x0408 0x04 0x01 |
| 846 | #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01F0 0x03F4 0x0000 0x05 0x00 |
| 847 | |
| 848 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01F4 0x03F8 0x0000 0x00 0x00 |
| 849 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01F4 0x03F8 0x0000 0x01 0x00 |
| 850 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01F4 0x03F8 0x0000 0x02 0x00 |
| 851 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01F4 0x03F8 0x0000 0x03 0x00 |
| 852 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01F4 0x03F8 0x0000 0x04 0x00 |
| 853 | #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01F4 0x03F8 0x0000 0x05 0x00 |
| 854 | |
| 855 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01F8 0x03FC 0x0000 0x00 0x00 |
| 856 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01F8 0x03FC 0x041C 0x01 0x01 |
| 857 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01F8 0x03FC 0x0000 0x02 0x00 |
| 858 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01F8 0x03FC 0x0000 0x03 0x00 |
| 859 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01F8 0x03FC 0x0000 0x04 0x00 |
| 860 | #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01F8 0x03FC 0x0000 0x05 0x00 |
| 861 | |
| 862 | #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01FC 0x0400 0x0000 0x00 0x00 |
| 863 | #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01FC 0x0400 0x0000 0x01 0x00 |
| 864 | #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01FC 0x0400 0x0000 0x05 0x00 |
| 865 | #endif /* __DTS_IMX95_PINFUNC_H */ |