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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm64 / freescale / imx8ulp.dtsi
blob: 2562a35286c208869d11d7fb970ac84638f45088 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6#include <dt-bindings/clock/imx8ulp-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/power/imx8ulp-power.h>
10#include <dt-bindings/thermal/thermal.h>
11
12#include "imx8ulp-pinfunc.h"
13
14/ {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpiod;
22 gpio1 = &gpioe;
23 gpio2 = &gpiof;
24 mmc0 = &usdhc0;
25 mmc1 = &usdhc1;
26 mmc2 = &usdhc2;
27 serial0 = &lpuart4;
28 serial1 = &lpuart5;
29 serial2 = &lpuart6;
30 serial3 = &lpuart7;
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]31 spi0 = &lpspi4;
32 spi1 = &lpspi5;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]33 };
34
35 cpus {
36 #address-cells = <2>;
37 #size-cells = <0>;
38
39 A35_0: cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a35";
42 reg = <0x0 0x0>;
43 enable-method = "psci";
44 next-level-cache = <&A35_L2>;
45 cpu-idle-states = <&cpu_sleep>;
46 };
47
48 A35_1: cpu@1 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a35";
51 reg = <0x0 0x1>;
52 enable-method = "psci";
53 next-level-cache = <&A35_L2>;
54 cpu-idle-states = <&cpu_sleep>;
55 };
56
57 A35_L2: l2-cache0 {
58 compatible = "cache";
59 cache-level = <2>;
60 cache-unified;
61 };
62
63 idle-states {
64 entry-method = "psci";
65
66 cpu_sleep: cpu-sleep {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x0>;
69 local-timer-stop;
70 entry-latency-us = <1000>;
71 exit-latency-us = <700>;
72 min-residency-us = <2700>;
73 };
74 };
75 };
76
77 gic: interrupt-controller@2d400000 {
78 compatible = "arm,gic-v3";
79 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
80 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
81 #interrupt-cells = <3>;
82 interrupt-controller;
83 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
84 };
85
86 pmu {
87 compatible = "arm,cortex-a35-pmu";
88 interrupt-parent = <&gic>;
89 interrupts = <GIC_PPI 7
90 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
91 interrupt-affinity = <&A35_0>, <&A35_1>;
92 };
93
94 psci {
95 compatible = "arm,psci-1.0";
96 method = "smc";
97 };
98
99 thermal-zones {
100 cpu-thermal {
101 polling-delay-passive = <250>;
102 polling-delay = <2000>;
103 thermal-sensors = <&scmi_sensor 0>;
104
105 trips {
106 cpu_alert0: trip0 {
107 temperature = <85000>;
108 hysteresis = <2000>;
109 type = "passive";
110 };
111
112 cpu_crit0: trip1 {
113 temperature = <95000>;
114 hysteresis = <2000>;
115 type = "critical";
116 };
117 };
118 };
119 };
120
121 timer {
122 compatible = "arm,armv8-timer";
123 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
125 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
126 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
127 };
128
129 frosc: clock-frosc {
130 compatible = "fixed-clock";
131 clock-frequency = <192000000>;
132 clock-output-names = "frosc";
133 #clock-cells = <0>;
134 };
135
136 lposc: clock-lposc {
137 compatible = "fixed-clock";
138 clock-frequency = <1000000>;
139 clock-output-names = "lposc";
140 #clock-cells = <0>;
141 };
142
143 rosc: clock-rosc {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
146 clock-output-names = "rosc";
147 #clock-cells = <0>;
148 };
149
150 sosc: clock-sosc {
151 compatible = "fixed-clock";
152 clock-frequency = <24000000>;
153 clock-output-names = "sosc";
154 #clock-cells = <0>;
155 };
156
157 sram@2201f000 {
158 compatible = "mmio-sram";
159 reg = <0x0 0x2201f000 0x0 0x1000>;
160
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges = <0 0x0 0x2201f000 0x1000>;
164
165 scmi_buf: scmi-sram-section@0 {
166 compatible = "arm,scmi-shmem";
167 reg = <0x0 0x400>;
168 };
169 };
170
171 firmware {
172 scmi {
173 compatible = "arm,scmi-smc";
174 arm,smc-id = <0xc20000fe>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 shmem = <&scmi_buf>;
178
179 scmi_devpd: protocol@11 {
180 reg = <0x11>;
181 #power-domain-cells = <1>;
182 };
183
184 scmi_sensor: protocol@15 {
185 reg = <0x15>;
186 #thermal-sensor-cells = <1>;
187 };
188 };
189 };
190
191 cm33: remoteproc-cm33 {
192 compatible = "fsl,imx8ulp-cm33";
193 status = "disabled";
194 };
195
196 soc: soc@0 {
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0x0 0x0 0x0 0x40000000>,
201 <0x60000000 0x0 0x60000000 0x1000000>;
202
203 s4muap: mailbox@27020000 {
204 compatible = "fsl,imx8ulp-mu-s4";
205 reg = <0x27020000 0x10000>;
206 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
207 #mbox-cells = <2>;
208 };
209
210 per_bridge3: bus@29000000 {
211 compatible = "simple-bus";
212 reg = <0x29000000 0x800000>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges;
216
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]217 edma1: dma-controller@29010000 {
218 compatible = "fsl,imx8ulp-edma";
219 reg = <0x29010000 0x210000>;
220 #dma-cells = <3>;
221 dma-channels = <32>;
222 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
255 <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
256 <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
257 <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
258 <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
259 <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
260 <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
261 <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
262 <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
263 <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
264 <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
265 <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
266 <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
267 <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
268 <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
269 <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
270 <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
271 clock-names = "dma", "ch00","ch01", "ch02", "ch03",
272 "ch04", "ch05", "ch06", "ch07",
273 "ch08", "ch09", "ch10", "ch11",
274 "ch12", "ch13", "ch14", "ch15",
275 "ch16", "ch17", "ch18", "ch19",
276 "ch20", "ch21", "ch22", "ch23",
277 "ch24", "ch25", "ch26", "ch27",
278 "ch28", "ch29", "ch30", "ch31";
279 };
280
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]281 mu: mailbox@29220000 {
282 compatible = "fsl,imx8ulp-mu";
283 reg = <0x29220000 0x10000>;
284 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
285 #mbox-cells = <2>;
286 status = "disabled";
287 };
288
289 mu3: mailbox@29230000 {
290 compatible = "fsl,imx8ulp-mu";
291 reg = <0x29230000 0x10000>;
292 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
294 #mbox-cells = <2>;
295 status = "disabled";
296 };
297
298 wdog3: watchdog@292a0000 {
299 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
300 reg = <0x292a0000 0x10000>;
301 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
303 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
304 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
305 timeout-sec = <40>;
306 };
307
308 cgc1: clock-controller@292c0000 {
309 compatible = "fsl,imx8ulp-cgc1";
310 reg = <0x292c0000 0x10000>;
311 #clock-cells = <1>;
312 };
313
314 pcc3: clock-controller@292d0000 {
315 compatible = "fsl,imx8ulp-pcc3";
316 reg = <0x292d0000 0x10000>;
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 };
320
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]321 crypto: crypto@292e0000 {
322 compatible = "fsl,sec-v4.0";
323 reg = <0x292e0000 0x10000>;
324 ranges = <0 0x292e0000 0x10000>;
325 #address-cells = <1>;
326 #size-cells = <1>;
327
328 sec_jr0: jr@1000 {
329 compatible = "fsl,sec-v4.0-job-ring";
330 reg = <0x1000 0x1000>;
331 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
332 };
333
334 sec_jr1: jr@2000 {
335 compatible = "fsl,sec-v4.0-job-ring";
336 reg = <0x2000 0x1000>;
337 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
338 };
339
340 sec_jr2: jr@3000 {
341 compatible = "fsl,sec-v4.0-job-ring";
342 reg = <0x3000 0x1000>;
343 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
344 };
345
346 sec_jr3: jr@4000 {
347 compatible = "fsl,sec-v4.0-job-ring";
348 reg = <0x4000 0x1000>;
349 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
350 };
351 };
352
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]353 tpm5: tpm@29340000 {
354 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
355 reg = <0x29340000 0x1000>;
356 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
358 <&pcc3 IMX8ULP_CLK_TPM5>;
359 clock-names = "ipg", "per";
360 status = "disabled";
361 };
362
363 lpi2c4: i2c@29370000 {
364 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
365 reg = <0x29370000 0x10000>;
366 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
368 <&pcc3 IMX8ULP_CLK_LPI2C4>;
369 clock-names = "per", "ipg";
370 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
371 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
372 assigned-clock-rates = <48000000>;
373 status = "disabled";
374 };
375
376 lpi2c5: i2c@29380000 {
377 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
378 reg = <0x29380000 0x10000>;
379 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
381 <&pcc3 IMX8ULP_CLK_LPI2C5>;
382 clock-names = "per", "ipg";
383 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
384 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
385 assigned-clock-rates = <48000000>;
386 status = "disabled";
387 };
388
389 lpuart4: serial@29390000 {
390 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
391 reg = <0x29390000 0x1000>;
392 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
394 clock-names = "ipg";
395 status = "disabled";
396 };
397
398 lpuart5: serial@293a0000 {
399 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
400 reg = <0x293a0000 0x1000>;
401 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
403 clock-names = "ipg";
404 status = "disabled";
405 };
406
407 lpspi4: spi@293b0000 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
411 reg = <0x293b0000 0x10000>;
412 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
414 <&pcc3 IMX8ULP_CLK_LPSPI4>;
415 clock-names = "per", "ipg";
416 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
417 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
418 assigned-clock-rates = <48000000>;
419 status = "disabled";
420 };
421
422 lpspi5: spi@293c0000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
426 reg = <0x293c0000 0x10000>;
427 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
429 <&pcc3 IMX8ULP_CLK_LPSPI5>;
430 clock-names = "per", "ipg";
431 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
432 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
433 assigned-clock-rates = <48000000>;
434 status = "disabled";
435 };
436 };
437
438 per_bridge4: bus@29800000 {
439 compatible = "simple-bus";
440 reg = <0x29800000 0x800000>;
441 #address-cells = <1>;
442 #size-cells = <1>;
443 ranges;
444
445 pcc4: clock-controller@29800000 {
446 compatible = "fsl,imx8ulp-pcc4";
447 reg = <0x29800000 0x10000>;
448 #clock-cells = <1>;
449 #reset-cells = <1>;
450 };
451
452 flexspi2: spi@29810000 {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]453 compatible = "nxp,imx8ulp-fspi";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]454 reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
455 reg-names = "fspi_base", "fspi_mmap";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
460 <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
461 clock-names = "fspi_en", "fspi";
462 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
463 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
464 status = "disabled";
465 };
466
467 lpi2c6: i2c@29840000 {
468 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
469 reg = <0x29840000 0x10000>;
470 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
472 <&pcc4 IMX8ULP_CLK_LPI2C6>;
473 clock-names = "per", "ipg";
474 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
475 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
476 assigned-clock-rates = <48000000>;
477 status = "disabled";
478 };
479
480 lpi2c7: i2c@29850000 {
481 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
482 reg = <0x29850000 0x10000>;
483 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
485 <&pcc4 IMX8ULP_CLK_LPI2C7>;
486 clock-names = "per", "ipg";
487 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
488 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
489 assigned-clock-rates = <48000000>;
490 status = "disabled";
491 };
492
493 lpuart6: serial@29860000 {
494 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
495 reg = <0x29860000 0x1000>;
496 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
498 clock-names = "ipg";
499 status = "disabled";
500 };
501
502 lpuart7: serial@29870000 {
503 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
504 reg = <0x29870000 0x1000>;
505 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
507 clock-names = "ipg";
508 status = "disabled";
509 };
510
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]511 sai4: sai@29880000 {
512 compatible = "fsl,imx8ulp-sai";
513 reg = <0x29880000 0x10000>;
514 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>,
516 <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
517 <&cgc1 IMX8ULP_CLK_DUMMY>;
518 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
519 dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
520 dma-names = "rx", "tx";
521 #sound-dai-cells = <0>;
522 fsl,dataline = <0 0x03 0x03>;
523 status = "disabled";
524 };
525
526 sai5: sai@29890000 {
527 compatible = "fsl,imx8ulp-sai";
528 reg = <0x29890000 0x10000>;
529 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>,
531 <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
532 <&cgc1 IMX8ULP_CLK_DUMMY>;
533 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
534 dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
535 dma-names = "rx", "tx";
536 #sound-dai-cells = <0>;
537 fsl,dataline = <0 0x0f 0x0f>;
538 status = "disabled";
539 };
540
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]541 iomuxc1: pinctrl@298c0000 {
542 compatible = "fsl,imx8ulp-iomuxc1";
543 reg = <0x298c0000 0x10000>;
544 };
545
546 usdhc0: mmc@298d0000 {
547 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
548 reg = <0x298d0000 0x10000>;
549 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
551 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
552 <&pcc4 IMX8ULP_CLK_USDHC0>;
553 clock-names = "ipg", "ahb", "per";
554 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
555 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
556 <&pcc4 IMX8ULP_CLK_USDHC0>;
557 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
558 assigned-clock-rates = <389283840>, <389283840>;
559 fsl,tuning-start-tap = <20>;
560 fsl,tuning-step = <2>;
561 bus-width = <4>;
562 status = "disabled";
563 };
564
565 usdhc1: mmc@298e0000 {
566 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
567 reg = <0x298e0000 0x10000>;
568 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
570 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
571 <&pcc4 IMX8ULP_CLK_USDHC1>;
572 clock-names = "ipg", "ahb", "per";
573 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
574 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
575 <&pcc4 IMX8ULP_CLK_USDHC1>;
576 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
577 assigned-clock-rates = <194641920>, <194641920>;
578 fsl,tuning-start-tap = <20>;
579 fsl,tuning-step = <2>;
580 bus-width = <4>;
581 status = "disabled";
582 };
583
584 usdhc2: mmc@298f0000 {
585 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
586 reg = <0x298f0000 0x10000>;
587 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
589 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
590 <&pcc4 IMX8ULP_CLK_USDHC2>;
591 clock-names = "ipg", "ahb", "per";
592 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
593 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
594 <&pcc4 IMX8ULP_CLK_USDHC2>;
595 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
596 assigned-clock-rates = <194641920>, <194641920>;
597 fsl,tuning-start-tap = <20>;
598 fsl,tuning-step = <2>;
599 bus-width = <4>;
600 status = "disabled";
601 };
602
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]603 usbotg1: usb@29900000 {
604 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
605 reg = <0x29900000 0x200>;
606 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&pcc4 IMX8ULP_CLK_USB0>;
608 power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
609 phys = <&usbphy1>;
610 fsl,usbmisc = <&usbmisc1 0>;
611 ahb-burst-config = <0x0>;
612 tx-burst-size-dword = <0x8>;
613 rx-burst-size-dword = <0x8>;
614 status = "disabled";
615 };
616
617 usbmisc1: usbmisc@29900200 {
618 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
619 "fsl,imx6q-usbmisc";
620 reg = <0x29900200 0x200>;
621 #index-cells = <1>;
622 status = "disabled";
623 };
624
625 usbphy1: usb-phy@29910000 {
626 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
627 reg = <0x29910000 0x10000>;
628 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
630 #phy-cells = <0>;
631 status = "disabled";
632 };
633
634 usbotg2: usb@29920000 {
635 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
636 reg = <0x29920000 0x200>;
637 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&pcc4 IMX8ULP_CLK_USB1>;
639 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
640 phys = <&usbphy2>;
641 fsl,usbmisc = <&usbmisc2 0>;
642 ahb-burst-config = <0x0>;
643 tx-burst-size-dword = <0x8>;
644 rx-burst-size-dword = <0x8>;
645 status = "disabled";
646 };
647
648 usbmisc2: usbmisc@29920200 {
649 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
650 "fsl,imx6q-usbmisc";
651 reg = <0x29920200 0x200>;
652 #index-cells = <1>;
653 status = "disabled";
654 };
655
656 usbphy2: usb-phy@29930000 {
657 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
658 reg = <0x29930000 0x10000>;
659 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
661 #phy-cells = <0>;
662 status = "disabled";
663 };
664
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]665 fec: ethernet@29950000 {
666 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
667 reg = <0x29950000 0x10000>;
668 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
669 interrupt-names = "int0";
670 fsl,num-tx-queues = <1>;
671 fsl,num-rx-queues = <1>;
672 status = "disabled";
673 };
674 };
675
676 gpioe: gpio@2d000000 {
677 compatible = "fsl,imx8ulp-gpio";
678 reg = <0x2d000000 0x1000>;
679 gpio-controller;
680 #gpio-cells = <2>;
681 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
683 interrupt-controller;
684 #interrupt-cells = <2>;
685 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
686 <&pcc4 IMX8ULP_CLK_PCTLE>;
687 clock-names = "gpio", "port";
688 gpio-ranges = <&iomuxc1 0 32 24>;
689 };
690
691 gpiof: gpio@2d010000 {
692 compatible = "fsl,imx8ulp-gpio";
693 reg = <0x2d010000 0x1000>;
694 gpio-controller;
695 #gpio-cells = <2>;
696 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
700 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
701 <&pcc4 IMX8ULP_CLK_PCTLF>;
702 clock-names = "gpio", "port";
703 gpio-ranges = <&iomuxc1 0 64 32>;
704 };
705
706 per_bridge5: bus@2d800000 {
707 compatible = "simple-bus";
708 reg = <0x2d800000 0x800000>;
709 #address-cells = <1>;
710 #size-cells = <1>;
711 ranges;
712
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]713 edma2: dma-controller@2d800000 {
714 compatible = "fsl,imx8ulp-edma";
715 reg = <0x2d800000 0x210000>;
716 #dma-cells = <3>;
717 dma-channels = <32>;
718 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
751 <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
752 <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
753 <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
754 <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
755 <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
756 <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
757 <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
758 <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
759 <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
760 <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
761 <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
762 <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
763 <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
764 <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
765 <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
766 <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
767 clock-names = "dma", "ch00","ch01", "ch02", "ch03",
768 "ch04", "ch05", "ch06", "ch07",
769 "ch08", "ch09", "ch10", "ch11",
770 "ch12", "ch13", "ch14", "ch15",
771 "ch16", "ch17", "ch18", "ch19",
772 "ch20", "ch21", "ch22", "ch23",
773 "ch24", "ch25", "ch26", "ch27",
774 "ch28", "ch29", "ch30", "ch31";
775 };
776
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]777 cgc2: clock-controller@2da60000 {
778 compatible = "fsl,imx8ulp-cgc2";
779 reg = <0x2da60000 0x10000>;
780 #clock-cells = <1>;
781 };
782
783 pcc5: clock-controller@2da70000 {
784 compatible = "fsl,imx8ulp-pcc5";
785 reg = <0x2da70000 0x10000>;
786 #clock-cells = <1>;
787 #reset-cells = <1>;
788 };
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]789
790 sai6: sai@2da90000 {
791 compatible = "fsl,imx8ulp-sai";
792 reg = <0x2da90000 0x10000>;
793 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>,
795 <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
796 <&cgc1 IMX8ULP_CLK_DUMMY>;
797 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
798 dmas = <&edma2 71 0 1>, <&edma2 72 0 0>;
799 dma-names = "rx", "tx";
800 #sound-dai-cells = <0>;
801 fsl,dataline = <0 0x0f 0x0f>;
802 status = "disabled";
803 };
804
805 sai7: sai@2daa0000 {
806 compatible = "fsl,imx8ulp-sai";
807 reg = <0x2daa0000 0x10000>;
808 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>,
810 <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
811 <&cgc1 IMX8ULP_CLK_DUMMY>;
812 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
813 dmas = <&edma2 73 0 1>, <&edma2 74 0 0>;
814 dma-names = "rx", "tx";
815 #sound-dai-cells = <0>;
816 fsl,dataline = <0 0x0f 0x0f>;
817 status = "disabled";
818 };
819
820 spdif: spdif@2dab0000 {
821 compatible = "fsl,imx8ulp-spdif";
822 reg = <0x2dab0000 0x10000>;
823 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */
825 <&sosc>, /* 0, extal */
826 <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */
827 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */
828 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */
829 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */
830 <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */
831 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */
832 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */
833 <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */
834 clock-names = "core", "rxtx0",
835 "rxtx1", "rxtx2",
836 "rxtx3", "rxtx4",
837 "rxtx5", "rxtx6",
838 "rxtx7", "spba";
839 dmas = <&edma2 75 0 5>, <&edma2 76 0 4>;
840 dma-names = "rx", "tx";
841 status = "disabled";
842 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]843 };
844
845 gpiod: gpio@2e200000 {
846 compatible = "fsl,imx8ulp-gpio";
847 reg = <0x2e200000 0x1000>;
848 gpio-controller;
849 #gpio-cells = <2>;
850 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
854 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
855 <&pcc5 IMX8ULP_CLK_RGPIOD>;
856 clock-names = "gpio", "port";
857 gpio-ranges = <&iomuxc1 0 0 24>;
858 };
859 };
860};